From patchwork Wed Nov 28 22:33:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 10703569 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A25DF15A7 for ; Wed, 28 Nov 2018 22:36:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 927992BA5B for ; Wed, 28 Nov 2018 22:36:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85E682DFA9; Wed, 28 Nov 2018 22:36:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2E4732BA5B for ; Wed, 28 Nov 2018 22:36:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=bVPdMgONU1+5VtnPRJlqPqqOB1tnPFsGl2Nct/Ry6EE=; b=R0kNRnNtBKzx6KqWFpykHKC+/t oeG00N9ZFn3vLQ6phQoSDsIuGh9YiEFfCflcoyCwXZRXDk1ROgd1bG2jNLi+eu1W4GQX3kv8rWkDZ lwyECQMBm3BuSNPXkxfAGom8OELW9JIA1AdiTNV74qhRtXFtqih2EZv3FYhLYwWv3MOHsxpY82tAf GeEeR93LZG4+KlosvJsfejgrBaAY5cr/Pib9ZAHc55R1KpuRUzjzy6A2d+ycufM5Avk44VzEcIdfW G/U5sXAOe68Rumrz+ySZTiji+7DYzau6zMErNQj1j85PnIv0zBrtX03MnsmOvf/A7T68zfJoQH8o5 Ce/kYEBA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gS8RT-0008EI-Mb; Wed, 28 Nov 2018 22:36:23 +0000 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gS8Ph-0005M2-Cf for linux-arm-kernel@lists.infradead.org; Wed, 28 Nov 2018 22:34:38 +0000 Received: by mail-wm1-x341.google.com with SMTP id r24so364794wmh.0 for ; Wed, 28 Nov 2018 14:34:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6Tg/Nlf4DVosGXWUAPR1HKg7aUMJ7+jsissUOrruo7A=; b=T+prGM+Wav3wTg9CrhaN6IBiHW7sSC3S8hk8BKdsnqYhOSLC4also0ykf7PRi51zET xkccAf4VylnY1bBO6jtOcJccnHEAeHcR7bxdviopsbJbyQbIeE4diIHEdGH8SUU5Quvq CZJDUkyg8upBkaopeimQfpf0qbSzUFQCHPivOHdCaVcopJWPg4wTZytLdI6yy7DikpnG ehID3LNWYUIuDDOAe/2H1Hkcpb2WPegW5mz0eM2eBPhQsTQ/F7SBs5EXqar+ZXyMwdHb BxxjESPnaDCCQLpL2IyFqIEfVi3j4RLX/Fk7pPLQc2m7HjMMrG7Ubdn/YMOSW7Ase/6j khYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6Tg/Nlf4DVosGXWUAPR1HKg7aUMJ7+jsissUOrruo7A=; b=Atg+C/dCmUxAseJ7jByo3MFpzX7HHHQ+nFAh40A851ltcSgVJC8RGD7vbVMiXUgvW5 6kDlgC34TM8fJMVxdkxnC10CQNuqjuPQg/QSaoEgA25WrgrEh6aI39qwsQQ7Fgfe2iYp +utu+YwIkgCDozBpLdEfSogCoblkKowD7pbDs66YB5xZ94FwRhwZXL8wOoWSSceckOED 3dMdR5FHbOYEaHceHqWphQu+Hf3p+YpVVweeODsYkD4H/aadt/HDuCBcApse1rgLajQt B2Oa05nkN3qJwN3JYmz79kF8d0CWhX7bA4bzY5vdjFNXuYqYNMGXwBsreKTfPooB9MYj q9Iw== X-Gm-Message-State: AA+aEWZfwlLi975Y9w+aZNrnZaOZngXoYzvTBchsWhI43mmQ0HT3nuaZ qNqGN5uSyKGENX+gJ/BSRGQ= X-Google-Smtp-Source: AFSGD/UctLgq76GTpB0m7Ls8ReOPiT8XNESh/qC8F1dm29hUTsatIooTlNOvUV3pkEwgDFguxiH0sg== X-Received: by 2002:a1c:e287:: with SMTP id z129mr131642wmg.71.1543444461628; Wed, 28 Nov 2018 14:34:21 -0800 (PST) Received: from ThinkPad.home ([185.219.177.239]) by smtp.gmail.com with ESMTPSA id g198sm180244wmd.23.2018.11.28.14.34.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:34:21 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v5 06/17] irqchip/sun4i: Move IC specific register offsets to struct Date: Thu, 29 Nov 2018 01:33:16 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_143433_626958_16D3399B X-CRM114-Status: GOOD ( 16.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mesih Kilinc , Julian Calaby , Linus Walleij , Daniel Lezcano , Russell King , Marc Zyngier , Chen-Yu Tsai , Rob Herring , Maxime Ripard , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves IC specific register offsets to sun4i_irq_chip_data struct in order to support different chips. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 0c32506..507f4e3 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -28,12 +28,16 @@ #define SUN4I_IRQ_NMI_CTRL_REG 0x0c #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x) #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x) -#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x) -#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG(data, x) ((data)->enable_reg_offset + 0x4 * x) +#define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) +#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 +#define SUN4I_IRQ_MASK_REG_OFFSET 0x50 struct sun4i_irq_chip_data { void __iomem *irq_base; struct irq_domain *irq_domain; + u32 enable_reg_offset; + u32 mask_reg_offset; }; static struct sun4i_irq_chip_data *irq_ic_data; @@ -57,9 +61,10 @@ static void sun4i_irq_mask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val & ~(1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static void sun4i_irq_unmask(struct irq_data *irqd) @@ -69,9 +74,10 @@ static void sun4i_irq_unmask(struct irq_data *irqd) int reg = irq / 32; u32 val; - val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + val = readl(irq_ic_data->irq_base + + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); writel(val | (1 << irq_off), - irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg)); + irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, reg)); } static struct irq_chip sun4i_irq_chip = { @@ -105,20 +111,23 @@ static int __init sun4i_of_init(struct device_node *node, return -ENOMEM; } + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", node); /* Disable all interrupts */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2)); /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */ - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1)); - writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1)); + writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2)); /* Clear all the pending interrupts */ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));