From patchwork Wed Feb 3 17:11:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Glauber X-Patchwork-Id: 8205641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 42D169F38B for ; Wed, 3 Feb 2016 17:15:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 64F822011B for ; Wed, 3 Feb 2016 17:15:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 302752010F for ; Wed, 3 Feb 2016 17:15:02 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR0zr-0005rn-3S; Wed, 03 Feb 2016 17:13:39 +0000 Received: from mail-wm0-f67.google.com ([74.125.82.67]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aR0z6-0005Dg-NN for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2016 17:12:57 +0000 Received: by mail-wm0-f67.google.com with SMTP id 128so8321499wmz.3 for ; Wed, 03 Feb 2016 09:12:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0eSMhwhJH1wjxCW3NQZSzrpo9EocmJam26ZQ2EuCBU0=; b=OvWnbIWrmvJgPUMk21BHT9tdJOl9rHRJAqYbrQTzZAPXI4L/VeMwGSkrn7O9EQ6yyO sD+zbIScxxLy8xMcE4gDpnRGK4Qd10ce40bco+1ZJpNWmZmHImLZcWuA8rzK7F6TqSf7 FRuv0iOKqzBiYJxWwVAgZAjvTF/xyi7H2MuKoErTnC7VXKvi2udMkFIRYBQwkdlsgxlD bfsgBgT+Rn+6vswIITQT1sF6ujd68Q/i9znTSq3e8EGYa9FnNUDL6R4+5rz5erS6lSx1 Mza3yRbS5MW6jPI0GAeSk5pqIE3GRQ+JLcWTxsc2K8cC4siqs05CtbUBwMQCIuLzhDFc /KPQ== X-Gm-Message-State: AG10YOTCU/31XHNcom1SAlA3B7+fbBjMJHgSoeRwIuhzbIHFKkMuYbeRCmns5YPTNwEnrA== X-Received: by 10.194.179.71 with SMTP id de7mr3026645wjc.119.1454519552688; Wed, 03 Feb 2016 09:12:32 -0800 (PST) Received: from wintermute.fritz.box (HSI-KBW-46-223-158-223.hsi.kabel-badenwuerttemberg.de. [46.223.158.223]) by smtp.gmail.com with ESMTPSA id u72sm8877096wmd.16.2016.02.03.09.12.31 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Feb 2016 09:12:32 -0800 (PST) From: Jan Glauber To: Will Deacon , Mark Rutland Subject: [PATCH v3 4/5] arm64/perf: Enable PMCR long cycle counter bit Date: Wed, 3 Feb 2016 18:11:59 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160203_091253_210167_5D50E816 X-CRM114-Status: GOOD ( 16.11 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jan Glauber MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With the long cycle counter bit (LC) disabled the cycle counter is not working on ThunderX SOC (ThunderX only implements Aarch64). Also, according to documentation LC == 0 is deprecated. To keep the code simple the patch does not introduce 64 bit wide counter functions. Instead writing the cycle counter always sets the upper 32 bits so overflow interrupts are generated as before. Original patch from Andrew Pinksi Signed-off-by: Jan Glauber --- arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index c038e4e..5e4275e 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -405,6 +405,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = { #define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */ #define ARMV8_PMCR_X (1 << 4) /* Export to ETM */ #define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define ARMV8_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */ #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */ #define ARMV8_PMCR_N_MASK 0x1f #define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */ @@ -494,9 +495,16 @@ static inline void armv8pmu_write_counter(struct perf_event *event, u32 value) if (!armv8pmu_counter_valid(cpu_pmu, idx)) pr_err("CPU%u writing wrong counter %d\n", smp_processor_id(), idx); - else if (idx == ARMV8_IDX_CYCLE_COUNTER) - asm volatile("msr pmccntr_el0, %0" :: "r" (value)); - else if (armv8pmu_select_counter(idx) == idx) + else if (idx == ARMV8_IDX_CYCLE_COUNTER) { + /* + * Set the upper 32bits as this is a 64bit counter but we only + * count using the lower 32bits and we want an interrupt when + * it overflows. + */ + u64 value64 = 0xffffffff00000000ULL | value; + + asm volatile("msr pmccntr_el0, %0" :: "r" (value64)); + } else if (armv8pmu_select_counter(idx) == idx) asm volatile("msr pmxevcntr_el0, %0" :: "r" (value)); } @@ -768,8 +776,11 @@ static void armv8pmu_reset(void *info) armv8pmu_disable_intens(idx); } - /* Initialize & Reset PMNC: C and P bits. */ - armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C); + /* + * Initialize & Reset PMNC. Request overflow on 64 bit but + * cheat in armv8pmu_write_counter(). + */ + armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C | ARMV8_PMCR_LC); } static int armv8_pmuv3_map_event(struct perf_event *event)