From patchwork Thu May 28 07:29:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 6496501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7ED4C9F1CC for ; Thu, 28 May 2015 07:33:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7B92720637 for ; Thu, 28 May 2015 07:33:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8565120635 for ; Thu, 28 May 2015 07:33:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxsHZ-00066o-Lz; Thu, 28 May 2015 07:31:13 +0000 Received: from mail-pa0-f41.google.com ([209.85.220.41]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YxsGx-0004u0-DN for linux-arm-kernel@lists.infradead.org; Thu, 28 May 2015 07:30:36 +0000 Received: by paza2 with SMTP id a2so17301344paz.3 for ; Thu, 28 May 2015 00:30:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=zKam8fzvYnjwWp3hQGvZFNbzTJ2MLJ/71UVmN9eQ/Qc=; b=Zbh6QkqGcXN3tei4diLWSK4hCN2dYkhpkG0YxlW8WtBAV76uKtI3Vw6jxIVRUeANaC NX/ar8rh+SaS30k7v5pwsNsePxPUwE7S+YBB+yyoQrALdvfEtN6Vln1dtO1ysH/9A9v/ LTfyY5a/4yQwHoBjodCxEexBRFzwk/IChut4y+Wj9OLtkrZyd8H1/oRP2VOrk9bszBNV rQks+FugEjTty6OPvhpcUk2qcbH7Itpkp5whGXKHmvdJsQveAcehL6r17kTyeqtwkEUT bio1YupW8RZ6gypt8MmvQyfATL8D8SsT3DSidXz28XLPwf03X2WgzBMxWDG1oGWsCMEd p1BA== X-Gm-Message-State: ALoCoQm8QuZC4QE/X4hbNmCbprrgZ+faBe4wKfq6qFPG7m9n4URl3jUbjz52cyJpz0tIHMhj7RcW X-Received: by 10.66.168.105 with SMTP id zv9mr2884375pab.121.1432798213954; Thu, 28 May 2015 00:30:13 -0700 (PDT) Received: from localhost ([122.167.219.251]) by mx.google.com with ESMTPSA id cp10sm1336701pdb.44.2015.05.28.00.30.12 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 00:30:13 -0700 (PDT) From: Viresh Kumar To: Rafael Wysocki , rob.herring@linaro.org Subject: [PATCH V6 2/3] OPP: Allow multiple OPP tables to be passed via DT Date: Thu, 28 May 2015 12:59:56 +0530 Message-Id: X-Mailer: git-send-email 2.4.0 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150528_003035_518341_735B1A4E X-CRM114-Status: GOOD ( 10.58 ) X-Spam-Score: -0.7 (/) Cc: nm@ti.com, devicetree@vger.kernel.org, kesavan.abhilash@gmail.com, linaro-kernel@lists.linaro.org, ta.omasab@gmail.com, khilman@linaro.org, linux-pm@vger.kernel.org, viswanath.puttagunta@linaro.org, Viresh Kumar , santosh.shilimkar@oracle.com, sboyd@codeaurora.org, olof@lixom.net, broonie@kernel.org, mike.turquette@linaro.org, Sudeep.Holla@arm.com, grant.likely@linaro.org, arnd.bergmann@linaro.org, thomas.petazzoni@free-electrons.com, linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some platforms (Like Qualcomm's SoCs), it is not decided until runtime on what OPPs to use. The OPP tables can be fixed at compile time, but which table to use is found out only after reading some efuses (sort of an prom) and knowing characteristics of the SoC. To support such platform we need to pass multiple OPP tables per device and hardware should be able to choose one and only one table out of those. Update OPP-v2 bindings to support that. Acked-by: Nishanth Menon Reviewed-by: Stephen Boyd Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/power/opp.txt | 52 +++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 0ca96e73d2a3..f6f75545149e 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -45,6 +45,9 @@ Devices supporting OPPs must set their "operating-points-v2" property with phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. +Devices may want to choose OPP tables at runtime and so can provide a list of +phandles here. But only *one* of them should be chosen at runtime. + If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". @@ -63,6 +66,9 @@ This describes the OPPs belonging to a device. This node can have following reference an OPP. Optional properties: +- opp-name: Name of the OPP table, to uniquely identify it if more than one OPP + table is supplied in "operating-points-v2" property of device. + - opp-shared: Indicates that device nodes using this OPP Table Node's phandle switch their DVFS state together, i.e. they share clock/voltage/current lines. Missing property means devices have independent clock/voltage/current lines, @@ -396,3 +402,49 @@ Example 4: Handling multiple regulators }; }; }; + +Example 5: Multiple OPP tables + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + opp-supply = <&cpu_supply> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; + }; + }; + + cpu0_opp_table_slow: opp_table_slow { + compatible = "operating-points-v2"; + opp-name = "slow"; + opp-shared; + + opp00 { + opp-hz = <600000000>; + ... + }; + + opp01 { + opp-hz = <800000000>; + ... + }; + }; + + cpu0_opp_table_fast: opp_table_fast { + compatible = "operating-points-v2"; + opp-name = "fast"; + opp-shared; + + opp10 { + opp-hz = <1000000000>; + ... + }; + + opp11 { + opp-hz = <1100000000>; + ... + }; + }; +};