| Message ID | eded393f4b508a1f377f9af6859a3b82a6787e1c.1527244201.git.viresh.kumar@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Fri, May 25, 2018 at 04:01:52PM +0530, Viresh Kumar wrote: > The cooling device properties, like "#cooling-cells" and > "dynamic-power-coefficient", should either be present for all the CPUs > of a cluster or none. If these are present only for a subset of CPUs of > a cluster then things will start falling apart as soon as the CPUs are > brought online in a different order. For example, this will happen > because the operating system looks for such properties in the CPU node > it is trying to bring up, so that it can register a cooling device. > > Add such missing properties. > > Fix other missing properties (clocks, OPP, clock latency) as well to > make it all work. > > Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> The prefix should be sunxi and not sun, but it looks good to me otherwise. Let me know what your preferred merge method is. Maxime
On 28-05-18, 10:44, Maxime Ripard wrote: > Hi, > > On Fri, May 25, 2018 at 04:01:52PM +0530, Viresh Kumar wrote: > > The cooling device properties, like "#cooling-cells" and > > "dynamic-power-coefficient", should either be present for all the CPUs > > of a cluster or none. If these are present only for a subset of CPUs of > > a cluster then things will start falling apart as soon as the CPUs are > > brought online in a different order. For example, this will happen > > because the operating system looks for such properties in the CPU node > > it is trying to bring up, so that it can register a cooling device. > > > > Add such missing properties. > > > > Fix other missing properties (clocks, OPP, clock latency) as well to > > make it all work. > > > > Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> > > The prefix should be sunxi and not sun, but it looks good to me > otherwise. > > Let me know what your preferred merge method is. Please pick it up directly and send it as part of your pull request. Do you want me to resend or can you fix the $subject ? Thanks.
Hi, On Mon, May 28, 2018 at 04:27:34PM +0530, Viresh Kumar wrote: > On 28-05-18, 10:44, Maxime Ripard wrote: > > Hi, > > > > On Fri, May 25, 2018 at 04:01:52PM +0530, Viresh Kumar wrote: > > > The cooling device properties, like "#cooling-cells" and > > > "dynamic-power-coefficient", should either be present for all the CPUs > > > of a cluster or none. If these are present only for a subset of CPUs of > > > a cluster then things will start falling apart as soon as the CPUs are > > > brought online in a different order. For example, this will happen > > > because the operating system looks for such properties in the CPU node > > > it is trying to bring up, so that it can register a cooling device. > > > > > > Add such missing properties. > > > > > > Fix other missing properties (clocks, OPP, clock latency) as well to > > > make it all work. > > > > > > Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> > > > > The prefix should be sunxi and not sun, but it looks good to me > > otherwise. > > > > Let me know what your preferred merge method is. > > Please pick it up directly and send it as part of your pull request. > Do you want me to resend or can you fix the $subject ? I just tried to apply it, and it failed. We have usually two different PR for the H3 SoCs and the others. Could you split the H3 in a separate patch (and fix the subject in the process?) Thanks! Maxime
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c72992556a86..debc0bf22ea3 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -119,18 +119,48 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e529e4ff2174..35372a0cfc8d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -122,6 +122,19 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPU>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 960000 1400000 + 912000 1400000 + 864000 1300000 + 720000 1200000 + 528000 1100000 + 312000 1000000 + 144000 1000000 + >; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index 8d278ee001e9..4e92741b24a7 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -132,21 +132,30 @@ }; cpu@1 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 41d57c76f290..9dff6887923c 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -84,21 +84,30 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; };
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> --- arch/arm/boot/dts/sun6i-a31.dtsi | 30 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 13 +++++++++++++ arch/arm/boot/dts/sun8i-a33.dtsi | 9 +++++++++ arch/arm/boot/dts/sun8i-h3.dtsi | 9 +++++++++ 4 files changed, 61 insertions(+)