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[178.255.168.35]) by mx.google.com with ESMTPSA id el6sm2905339wib.23.2014.11.14.02.52.14 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Fri, 14 Nov 2014 02:52:14 -0800 (PST) From: Michal Simek To: linux-arm-kernel@lists.infradead.org, Soren Brinkmann , Olof Johansson , Arnd Bergmann Subject: [PATCH v4 2/6] ARM: zynq: Extract slcr related functions out of common.h Date: Fri, 14 Nov 2014 11:52:03 +0100 Message-Id: X-Mailer: git-send-email 1.8.2.3 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20141114_025232_519199_A6B8156C X-CRM114-Status: GOOD ( 16.42 ) X-Spam-Score: 1.3 (+) Cc: Josh Cartwright , monstr@monstr.eu, Russell King , Peter Crosthwaite , linux-kernel@vger.kernel.org, Steffen Trumtrar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, T_RP_MATCHES_RCVD,T_TVD_MIME_NO_HEADERS,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Create topic headers not to share all functions. Signed-off-by: Michal Simek --- Changes in v4: - New patch in this series Changes in v3: None Changes in v2: None arch/arm/mach-zynq/common.c | 1 + arch/arm/mach-zynq/common.h | 9 --------- arch/arm/mach-zynq/platsmp.c | 1 + arch/arm/mach-zynq/slcr.c | 1 + arch/arm/mach-zynq/slcr.h | 29 +++++++++++++++++++++++++++++ 5 files changed, 32 insertions(+), 9 deletions(-) create mode 100644 arch/arm/mach-zynq/slcr.h -- 1.8.2.3 diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 45cb778b344d..947e72b79496 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -43,6 +43,7 @@ #include #include "common.h" +#include "slcr.h" #include "smp.h" #define ZYNQ_DEVCFG_MCTRL 0x80 diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 0667cc79f179..5557de83058a 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,15 +17,6 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -extern int zynq_slcr_init(void); -extern int zynq_early_slcr_init(void); -extern void zynq_slcr_system_reset(void); -extern void zynq_slcr_cpu_stop(int cpu); -extern void zynq_slcr_cpu_start(int cpu); -extern bool zynq_slcr_cpu_state_read(int cpu); -extern void zynq_slcr_cpu_state_write(int cpu, bool die); -extern u32 zynq_slcr_get_device_id(void); - extern void __iomem *zynq_scu_base; void zynq_pm_late_init(void); diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 5aa6b9ee95fc..717ba2b922b1 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -26,6 +26,7 @@ #include #include #include "common.h" +#include "slcr.h" #include "smp.h" /* diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index d4cb50cf97c0..40f8d7420334 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -20,6 +20,7 @@ #include #include #include "common.h" +#include "slcr.h" /* register offsets */ #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ diff --git a/arch/arm/mach-zynq/slcr.h b/arch/arm/mach-zynq/slcr.h new file mode 100644 index 000000000000..7b4edab666ee --- /dev/null +++ b/arch/arm/mach-zynq/slcr.h @@ -0,0 +1,29 @@ +/* + * This file contains common function prototypes to avoid externs + * in the c files. + * + * Copyright (C) 2014 Xilinx + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_ZYNQ_SLCR_H__ +#define __MACH_ZYNQ_SLCR_H__ + +extern int zynq_slcr_init(void); +extern int zynq_early_slcr_init(void); +extern void zynq_slcr_system_reset(void); +extern void zynq_slcr_cpu_stop(int cpu); +extern void zynq_slcr_cpu_start(int cpu); +extern bool zynq_slcr_cpu_state_read(int cpu); +extern void zynq_slcr_cpu_state_write(int cpu, bool die); +extern u32 zynq_slcr_get_device_id(void); + +#endif