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Wed, 7 Aug 2024 13:11:09 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , Subject: [PATCH v1 04/16] iommufd/selftest: Add IOMMU_VIOMMU_ALLOC test coverage Date: Wed, 7 Aug 2024 13:10:45 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DF:EE_|MW4PR12MB7287:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b0b893c-4e5f-4c01-5121-08dcb71d1e48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: awWw7lDXuN26WLfACyYwFuM5IrFvr/RPBhdQzfIT5SOVXlHsi1/6zU4UIEdc4fJjfQVdfJA9CYd0uXGFld5SnvalykA3g9tUr1G/dekp4sR4xJMn1ObRBt9rJXFDHBYf2K4pnnBE/8yjmLMCH3At6gqVA/Cy44guG8iJDoDGp5eSVrNCoaEWwA/CqoXBUzbqUUzwN8J5ngicqD/VvtKkYqFha8H/YqC0ILYz62uIdNutK1kuBSXGFni6qt/PDCHMfyXy+5guV717jVe7QlrtaObv8Ny2x9zecoRPrrYi/ESnK3SdGCfJ8lLmezpvUCFSOJoRmMDA5TlJsVqXRuYe8v/MNMNe0xcMAQihfDNN0v74btBP8Q4SJXGUuKreF8zkdYuCAaZp1RMNHEBT5kswcHpPG3Ej4+4AJ3YNC2nArhGrJ98iYBD5pAHIV3Q6Jtl5yQopcyViViNdh1XjOCKymvUluJQqONeeYMhqYIfB6ZR04sjbMdHROlcQ+75wNuVg8T5OG4dt6X4YoZMxOKj5Yz4zTet/yVcWwSj826xiabiytXq5pG0soQfp/nYIV3KtzCLxaaXoUkq2ZE5qx0mBksi4/3nHW44pt0paRkYEpPkixOTOY9yA5Ab4L0wucgYTge7xw+y/+dhEwEz3NceGlW98jKoVGNxdu6D28z3fBO2VNxgdwJZZ9FW6le2+/62zfd56dU2RYjRIbBQXimfs7PZCyAX9afLgXj9ReFHhftZJ1VP28+KG+9+7MpuwXVmmpcj+2q1jl173hO5qDmmgY3pDINJBwk+p36zX4FBRzDEiVIuJ4hyF1U7skDPHRdV3gAMNFm/RCmOrpejD04KHdptalImrtDrkVA+yu5jHDif+stSNHDhMja/lRAT/gO9ePQwmnKtnCr0tWrWnqaaEcI3LrW7RJvH7LlytB2mUZ06z/k/PxQWbJwfi9svnUIIbHv+GoxWCljfluSUV4eZLBVJgdXZeACNIo57sCK8TbIjFkPi/SST5051+c5Vg1H0PlqFaDZZWAeTT7Q3xWpI4Zg5v9iaJcC/HxODqf5k4e3X5z++qyr2TGo/ZVNaLIcX6q9s8FTajHIU33d/j7hrAe2wdfPow6w5BzPzZOfe/iKwFc7kwEgeucH4v6R8LBMYGiS2XF1jkQ3cVhZJjOVNWd1O3QwpgitEF/5vyEchyPaELlLNmXm3HLR+yXBnPTrdEpvmVp+PIjDiQUw5KIK4A1qGrU+Jp/L9bBGVGdfuSRCFECYDwuyELh4Bp4UY6RkEXwEJVZDmt9fCLHREsEYoBZgERgVnswIJCv7tcVLVWQlhvXBKkpWFz6DoNZXqWmSyt2om/Gn67ytvbfVlWlEmuVYdKY+eEZLMG8lFIQcCrinfwmn/7SCE68KHz4+l7xtMou+3vC/8scZnv4Wns5/ZjDc4sCe5noPuO8oEEAWwIOsSCO5ZUix+p8eVAGD+V0r6i X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 20:11:26.7726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b0b893c-4e5f-4c01-5121-08dcb71d1e48 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DF.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7287 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240807_131132_348364_84CDB8FA X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use IOMMU_VIOMMU_TYPE_DEFAULT to cover the new IOMMU_VIOMMU_ALLOC ioctl. Signed-off-by: Nicolin Chen --- tools/testing/selftests/iommu/iommufd.c | 35 +++++++++++++++++++ tools/testing/selftests/iommu/iommufd_utils.h | 28 +++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selftests/iommu/iommufd.c index 6343f4053bd4..5c770e94f299 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -554,6 +554,41 @@ TEST_F(iommufd_ioas, alloc_hwpt_nested) } } +TEST_F(iommufd_ioas, viommu_default) +{ + uint32_t dev_id = self->device_id; + uint32_t viommu_id = 0; + uint32_t hwpt_id = 0; + + if (dev_id) { + /* Negative test -- invalid hwpt */ + test_err_viommu_alloc(ENOENT, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + + /* Negative test -- not a nested parent hwpt */ + test_cmd_hwpt_alloc(dev_id, self->ioas_id, 0, &hwpt_id); + test_err_viommu_alloc(EINVAL, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + test_ioctl_destroy(hwpt_id); + + /* Allocate a nested parent HWP */ + test_cmd_hwpt_alloc(dev_id, self->ioas_id, + IOMMU_HWPT_ALLOC_NEST_PARENT, + &hwpt_id); + /* Negative test -- unsupported viommu type */ + test_err_viommu_alloc(EOPNOTSUPP, dev_id, hwpt_id, + 0xdead, &viommu_id); + /* Allocate a default type of viommu */ + test_cmd_viommu_alloc(dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + test_ioctl_destroy(viommu_id); + test_ioctl_destroy(hwpt_id); + } else { + test_err_viommu_alloc(ENOENT, dev_id, hwpt_id, + IOMMU_VIOMMU_TYPE_DEFAULT, &viommu_id); + } +} + TEST_F(iommufd_ioas, hwpt_attach) { /* Create a device attached directly to a hwpt */ diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/selftests/iommu/iommufd_utils.h index bc4556a48d82..810783d31ca5 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -771,3 +771,31 @@ static int _test_cmd_trigger_iopf(int fd, __u32 device_id, __u32 fault_fd) #define test_cmd_trigger_iopf(device_id, fault_fd) \ ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, fault_fd)) + +static int _test_cmd_viommu_alloc(int fd, __u32 device_id, __u32 hwpt_id, + __u32 type, __u32 flags, __u32 *viommu_id) +{ + struct iommu_viommu_alloc cmd = { + .size = sizeof(cmd), + .flags = flags, + .type = type, + .dev_id = device_id, + .hwpt_id = hwpt_id, + }; + int ret; + + ret = ioctl(fd, IOMMU_VIOMMU_ALLOC, &cmd); + if (ret) + return ret; + if (viommu_id) + *viommu_id = cmd.out_viommu_id; + return 0; +} + +#define test_cmd_viommu_alloc(device_id, hwpt_id, type, viommu_id) \ + ASSERT_EQ(0, _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, \ + type, 0, viommu_id)) +#define test_err_viommu_alloc(_errno, device_id, hwpt_id, type, viommu_id) \ + EXPECT_ERRNO(_errno, _test_cmd_viommu_alloc(self->fd, device_id, \ + hwpt_id, type, 0, \ + viommu_id))