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Received: from foss.arm.com ([217.140.101.70]) by merlin.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gCmJI-0001q9-Ms for linux-arm-kernel@lists.infradead.org; Wed, 17 Oct 2018 13:56:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71727EBD; Wed, 17 Oct 2018 06:56:15 -0700 (PDT) Received: from e110467-lin.cambridge.arm.com (unknown [10.1.196.75]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 69E123F5D3; Wed, 17 Oct 2018 06:56:14 -0700 (PDT) From: Robin Murphy To: will.deacon@arm.com Subject: [PATCH v5 2/2] iommu/arm-smmu-v3: Reunify arm_smmu_cmdq_issue_sync() Date: Wed, 17 Oct 2018 14:56:07 +0100 Message-Id: X-Mailer: git-send-email 2.19.1.dirty In-Reply-To: <61b4c3e5f1322dfe96ca2062a7fe058298340996.1539782799.git.robin.murphy@arm.com> References: <61b4c3e5f1322dfe96ca2062a7fe058298340996.1539782799.git.robin.murphy@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181017_095628_908842_143D7A9E X-CRM114-Status: GOOD ( 16.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew.murray@arm.com, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, thunder.leizhen@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now that both sync methods are more or less the same shape, we can save some code and levels of indirection by rolling them up together again, with just a couple of simple conditionals to discriminate the MSI and queue-polling specifics. Signed-off-by: Robin Murphy Signed-off-by: John Garry Reviewed-by: Andrew Murray Tested-by: John Garry --- drivers/iommu/arm-smmu-v3.c | 49 +++++++++---------------------------- 1 file changed, 12 insertions(+), 37 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index da8a91d116bf..36db63e3afcf 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -933,7 +933,7 @@ static void arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, * The difference between val and sync_idx is bounded by the maximum size of * a queue at 2^20 entries, so 32 bits is plenty for wrap-safe arithmetic. */ -static int __arm_smmu_sync_poll_msi(struct arm_smmu_device *smmu, u32 sync_idx) +static int arm_smmu_sync_poll_msi(struct arm_smmu_device *smmu, u32 sync_idx) { ktime_t timeout; u32 val; @@ -988,16 +988,17 @@ static int arm_smmu_sync_poll_cons(struct arm_smmu_device *smmu, u32 sync_idx, return -ETIMEDOUT; } -static int __arm_smmu_cmdq_issue_sync_msi(struct arm_smmu_device *smmu) +static void arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) { u64 cmd[CMDQ_ENT_DWORDS]; unsigned long flags; - struct arm_smmu_cmdq_ent ent = { - .opcode = CMDQ_OP_CMD_SYNC, - .sync = { - .msiaddr = cpu_to_le32(virt_to_phys(&smmu->sync_count)), - }, - }; + bool msi = (smmu->features & ARM_SMMU_FEAT_MSI) && + (smmu->features & ARM_SMMU_FEAT_COHERENCY); + struct arm_smmu_cmdq_ent ent = { .opcode = CMDQ_OP_CMD_SYNC }; + int ret, sync_idx, sync_gen; + + if (msi) + ent.sync.msiaddr = cpu_to_le32(virt_to_phys(&smmu->sync_count)); spin_lock_irqsave(&smmu->cmdq.lock, flags); @@ -1009,39 +1010,13 @@ static int __arm_smmu_cmdq_issue_sync_msi(struct arm_smmu_device *smmu) arm_smmu_cmdq_build_cmd(cmd, &ent); arm_smmu_cmdq_insert_cmd(smmu, cmd); } - - spin_unlock_irqrestore(&smmu->cmdq.lock, flags); - - return __arm_smmu_sync_poll_msi(smmu, ent.sync.msidata); -} - -static int __arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) -{ - u64 cmd[CMDQ_ENT_DWORDS]; - unsigned long flags; - struct arm_smmu_cmdq_ent ent = { .opcode = CMDQ_OP_CMD_SYNC }; - int sync_idx, sync_gen; - - arm_smmu_cmdq_build_cmd(cmd, &ent); - - spin_lock_irqsave(&smmu->cmdq.lock, flags); - if (smmu->prev_cmd_opcode != CMDQ_OP_CMD_SYNC) - arm_smmu_cmdq_insert_cmd(smmu, cmd); sync_idx = smmu->cmdq.q.prod; sync_gen = READ_ONCE(smmu->cmdq_generation); + spin_unlock_irqrestore(&smmu->cmdq.lock, flags); - return arm_smmu_sync_poll_cons(smmu, sync_idx, sync_gen); -} - -static void arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) -{ - int ret; - bool msi = (smmu->features & ARM_SMMU_FEAT_MSI) && - (smmu->features & ARM_SMMU_FEAT_COHERENCY); - - ret = msi ? __arm_smmu_cmdq_issue_sync_msi(smmu) - : __arm_smmu_cmdq_issue_sync(smmu); + ret = msi ? arm_smmu_sync_poll_msi(smmu, ent.sync.msidata) + : arm_smmu_sync_poll_cons(smmu, sync_idx, sync_gen); if (ret) dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout\n"); }