[0/4] Fixup register offsets to support per core L3 DCVS

Message

Sibi Sankar July 29, 2021, 6:04 p.m. UTC

Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache
frequency. The patch series re-arranges the cpufreq register offsets to
allow access for the L3 interconnect to implement per core control i.e.
the first 0x100 is now accessed by the L3 interconnect driver instead.

L3 interconnect provider node on SC7280 SoC:
epss_l3: interconnect@18590000 {
	compatible = "qcom,sc7280-epss-l3";
        reg = <0 0x18590000 0 0x1000>, <0 0x18591000 0 0x100>,
	      <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
	...
};

CPUFREQ node on SC7280 SoC:
cpufreq_hw: cpufreq@18591000 {
	compatible = "qcom,cpufreq-epss";
	reg = <0 0x18591100 0 0x900>,
	      <0 0x18592100 0 0x900>,
	      <0 0x18593100 0 0x900>;
	...
};

The patch series also prevents binding breakage by using the
SM8250/SM8350 EPSS compatible.

Sibi Sankar (4):
  dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
  cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS
  arm64: dts: qcom: sc7280: Fixup the cpufreq node
  arm64: dts: qcom: sm8350: Fixup the cpufreq node

 .../bindings/cpufreq/cpufreq-qcom-hw.txt           |  6 +++++-
 arch/arm64/boot/dts/qcom/sc7280.dtsi               |  6 +++---
 arch/arm64/boot/dts/qcom/sm8350.dtsi               |  9 ++++-----
 drivers/cpufreq/qcom-cpufreq-hw.c                  | 23 ++++++++++++++++++----
 4 files changed, 31 insertions(+), 13 deletions(-)