From patchwork Thu Jul 29 18:04:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 12409429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A86CEC4320A for ; Thu, 29 Jul 2021 18:05:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8417B60F48 for ; Thu, 29 Jul 2021 18:05:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231602AbhG2SFW (ORCPT ); Thu, 29 Jul 2021 14:05:22 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:30056 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230351AbhG2SFO (ORCPT ); Thu, 29 Jul 2021 14:05:14 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1627581911; h=Message-Id: Date: Subject: Cc: To: From: Sender; bh=jGAZNpvv9zROAVlHGnt4zPV0nfKI5c1XmksYWoQ4fn0=; b=JAPR5mekOLgex/Y+n7tzlWPnVslcB3Lk6Ab9/aNHbxa5JI+hu8twyGfvjVXaherDLLefgBGs Mp8mFpR9pigcFlUU+ftAAIV7M1AnjtseJYyy4YRFojSmiDkzEKGWk7lyNK2isogTeVIVWFXr 4DWWQKALp0HCZDKz4DkjKkeGJ/M= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-east-1.postgun.com with SMTP id 6102edcd1dd16c87885da9cf (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 29 Jul 2021 18:05:01 GMT Sender: sibis=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 85B93C43217; Thu, 29 Jul 2021 18:05:00 +0000 (UTC) Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id DC769C433D3; Thu, 29 Jul 2021 18:04:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DC769C433D3 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: sboyd@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, mka@chromium.org Cc: viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, tdas@codeaurora.org, Sibi Sankar Subject: [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Date: Thu, 29 Jul 2021 23:34:41 +0530 Message-Id: <1627581885-32165-1-git-send-email-sibis@codeaurora.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache frequency. The patch series re-arranges the cpufreq register offsets to allow access for the L3 interconnect to implement per core control i.e. the first 0x100 is now accessed by the L3 interconnect driver instead. L3 interconnect provider node on SC7280 SoC: epss_l3: interconnect@18590000 { compatible = "qcom,sc7280-epss-l3"; reg = <0 0x18590000 0 0x1000>, <0 0x18591000 0 0x100>, <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>; ... }; CPUFREQ node on SC7280 SoC: cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591100 0 0x900>, <0 0x18592100 0 0x900>, <0 0x18593100 0 0x900>; ... }; The patch series also prevents binding breakage by using the SM8250/SM8350 EPSS compatible. Sibi Sankar (4): dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS arm64: dts: qcom: sc7280: Fixup the cpufreq node arm64: dts: qcom: sm8350: Fixup the cpufreq node .../bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++----- drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++---- 4 files changed, 31 insertions(+), 13 deletions(-)