From patchwork Tue Feb 15 10:00:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 12746827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C50F1C3525A for ; Tue, 15 Feb 2022 10:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236243AbiBOKAz (ORCPT ); Tue, 15 Feb 2022 05:00:55 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236219AbiBOKAu (ORCPT ); Tue, 15 Feb 2022 05:00:50 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9C2D10E077; Tue, 15 Feb 2022 02:00:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644919241; x=1676455241; h=from:to:cc:subject:date:message-id; bh=lYN6Qt8tApo+mea5juR8zMaYnSACX0anmwkxsl1TNos=; b=Cg9ZfaWptoawplX5DPprpkQKtST1gKNBq7h+cl3OU5+UAFdLiTfjSwn9 6PraFl+iH2725PB3dCbxdPooLlVczplWVeqVx0iaYrDKF/YJ8O2ThdRQh HTZP7/8Do2lLomca0/VPZCc5fR1A23cMNjEuspT7TCsGUPFMEMfPj/cM9 U=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 15 Feb 2022 02:00:40 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 15 Feb 2022 02:00:38 -0800 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 15 Feb 2022 15:30:24 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 2A906466C; Tue, 15 Feb 2022 15:30:23 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, bjorn.andersson@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 0/7] Add APCS support for SDX65 Date: Tue, 15 Feb 2022 15:30:20 +0530 Message-Id: <1644919220-27041-1-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hello, Changes from v1: - Addressed Mani's comments and made necessary changes. - Removed the last patch from the series as it became redundant after making changes. This series adds APCS mailbox and clock support for SDX65. The APCS IP in SDX65 provides IPC and clock functionalities. Hence, mailbox support is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock driver "apcs-sdx65" is added. Thanks, Rohit Rohit Agarwal (7): dt-bindings: mailbox: Add binding for SDX65 APCS mailbox: qcom: Add support for SDX65 APCS IPC dt-bindings: clock: Add A7 PLL binding for SDX65 clk: qcom: Add A7 PLL support for SDX65 ARM: dts: qcom: sdx65: Add support for A7 PLL clock ARM: dts: qcom: sdx65: Add support for APCS block clk: qcom: Add SDX65 APCS clock controller support Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + arch/arm/boot/dts/qcom-sdx65.dtsi | 17 +++++++++++++++++ drivers/clk/qcom/Kconfig | 12 ++++++------ drivers/clk/qcom/a7-pll.c | 1 + drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +++++ 6 files changed, 32 insertions(+), 7 deletions(-)