[v5,0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P

Message

Mrinmay Sarkar Feb. 23, 2024, 2:03 p.m. UTC

Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
the requester is indicating that there no cache coherency issues exit
for the addressed memory on the host i.e., memory is not cached. But
in reality, requester cannot assume this unless there is a complete
control/visibility over the addressed memory on the host.

And worst case, if the memory is cached on the host, it may lead to
memory corruption issues. It should be noted that the caching of memory
on the host is not solely dependent on the NO_SNOOP attribute in TLP.

So to avoid the corruption, this patch overrides the NO_SNOOP attribute
by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
needed for other upstream supported platforms since they do not set
NO_SNOOP attribute by default.

This series is to enable cache snooping logic in both RC and EP driver
and add the "dma-coherent" property in dtsi to support cache coherency
in SA8775P platform.

Dependency
----------

Depends on:
https://lore.kernel.org/all/[e-mail]/
https://lore.kernel.org/all/[e-mail]/ [1]

V4 -> V5:
- Updated commit message in both Patch1 and patch2
- change variable name from no_snoop_override to
  enable_cache_snoop
- rebased patch2 on top of [1]

v3 -> v4:
- added new cfg(cfg_1_34_0) for SA8775P in both RC and EP driver.
- populated a flag in the data structures instead of doing
  of_device_is_compatible() in both RC and EP patch.
- update commit mesaage and added reveiwed-by tag in commit message
  in dtsi patch.

v2 -> v3:
- update commit message(8755 -> 8775).

v1 -> v2:
- update cover letter with explanation.
- define each of these bits and ORing at usage time rather than
  directly writing value in register.

Mrinmay Sarkar (3):
  PCI: qcom: Enable cache coherency for SA8775P RC
  PCI: qcom-ep: Enable cache coherency for SA8775P EP
  arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent

 arch/arm64/boot/dts/qcom/sa8775p.dtsi     |  1 +
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 20 +++++++++++++++++---
 drivers/pci/controller/dwc/pcie-qcom.c    | 20 +++++++++++++++++++-
 3 files changed, 37 insertions(+), 4 deletions(-)

Comments

Krzysztof Kozlowski Feb. 24, 2024, 10:19 a.m. UTC | #1

On 23/02/2024 15:03, Mrinmay Sarkar wrote:
> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
> the requester is indicating that there no cache coherency issues exit
> for the addressed memory on the host i.e., memory is not cached. But
> in reality, requester cannot assume this unless there is a complete
> control/visibility over the addressed memory on the host.
> 
> And worst case, if the memory is cached on the host, it may lead to
> memory corruption issues. It should be noted that the caching of memory
> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
> 
> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
> needed for other upstream supported platforms since they do not set
> NO_SNOOP attribute by default.
> 
> This series is to enable cache snooping logic in both RC and EP driver
> and add the "dma-coherent" property in dtsi to support cache coherency
> in SA8775P platform.

Please confirm that your patchset passes 100% dtbs_check.

Best regards,
Krzysztof

Mrinmay Sarkar Feb. 28, 2024, 1:07 p.m. UTC | #2

On 2/24/2024 3:49 PM, Krzysztof Kozlowski wrote:
> On 23/02/2024 15:03, Mrinmay Sarkar wrote:
>> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
>> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
>> the requester is indicating that there no cache coherency issues exit
>> for the addressed memory on the host i.e., memory is not cached. But
>> in reality, requester cannot assume this unless there is a complete
>> control/visibility over the addressed memory on the host.
>>
>> And worst case, if the memory is cached on the host, it may lead to
>> memory corruption issues. It should be noted that the caching of memory
>> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
>>
>> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
>> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
>> needed for other upstream supported platforms since they do not set
>> NO_SNOOP attribute by default.
>>
>> This series is to enable cache snooping logic in both RC and EP driver
>> and add the "dma-coherent" property in dtsi to support cache coherency
>> in SA8775P platform.
> Please confirm that your patchset passes 100% dtbs_check.
>
> Best regards,
> Krzysztof

I have run dtbs_check and it is passing.

Thanks
Mrinmay

>

Krzysztof Kozlowski Feb. 28, 2024, 2:02 p.m. UTC | #3

On 28/02/2024 14:07, Mrinmay Sarkar wrote:
> 
> On 2/24/2024 3:49 PM, Krzysztof Kozlowski wrote:
>> On 23/02/2024 15:03, Mrinmay Sarkar wrote:
>>> Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
>>> in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
>>> the requester is indicating that there no cache coherency issues exit
>>> for the addressed memory on the host i.e., memory is not cached. But
>>> in reality, requester cannot assume this unless there is a complete
>>> control/visibility over the addressed memory on the host.
>>>
>>> And worst case, if the memory is cached on the host, it may lead to
>>> memory corruption issues. It should be noted that the caching of memory
>>> on the host is not solely dependent on the NO_SNOOP attribute in TLP.
>>>
>>> So to avoid the corruption, this patch overrides the NO_SNOOP attribute
>>> by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
>>> needed for other upstream supported platforms since they do not set
>>> NO_SNOOP attribute by default.
>>>
>>> This series is to enable cache snooping logic in both RC and EP driver
>>> and add the "dma-coherent" property in dtsi to support cache coherency
>>> in SA8775P platform.
>> Please confirm that your patchset passes 100% dtbs_check.
>>
>> Best regards,
>> Krzysztof
> 
> I have run dtbs_check and it is passing.

Hm, last time I checked dma-coherent was not allowed.

Best regards,
Krzysztof