From patchwork Fri Sep 14 15:19:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10600929 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 043E814BD for ; Fri, 14 Sep 2018 15:19:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC3CE2B959 for ; Fri, 14 Sep 2018 15:19:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D052F2B9C0; Fri, 14 Sep 2018 15:19:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C7042B959 for ; Fri, 14 Sep 2018 15:19:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727749AbeINUei (ORCPT ); Fri, 14 Sep 2018 16:34:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:41318 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726902AbeINUei (ORCPT ); Fri, 14 Sep 2018 16:34:38 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BAFDD60881; Fri, 14 Sep 2018 15:19:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536938379; bh=IC89zY6Rne4qTaRWSM8NvOtkERNpp2OsKrBBkBPD4Dg=; h=From:To:Cc:Subject:Date:From; b=Ny08ouk2tOYQI0Egtf4IcdiUm9Ptgj9895vUFTQ0mrvxpCb8pIlR/WIeTmfGPP5rw /9wcJMPB2kQPdIDh6D6d0huByzrB6ecxTkGHqJvcJxOmpGxMAyyeI6+TyEt/LeUJfg DjULd9SzKG1neeBi7SN5yEpknpu97rV/tbnOr53w= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 08C6660711; Fri, 14 Sep 2018 15:19:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1536938379; bh=IC89zY6Rne4qTaRWSM8NvOtkERNpp2OsKrBBkBPD4Dg=; h=From:To:Cc:Subject:Date:From; b=Ny08ouk2tOYQI0Egtf4IcdiUm9Ptgj9895vUFTQ0mrvxpCb8pIlR/WIeTmfGPP5rw /9wcJMPB2kQPdIDh6D6d0huByzrB6ecxTkGHqJvcJxOmpGxMAyyeI6+TyEt/LeUJfg DjULd9SzKG1neeBi7SN5yEpknpu97rV/tbnOr53w= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 08C6660711 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: robdclark@gmail.com Subject: [PATCH 0/6] Add a6xx GPU state capture Date: Fri, 14 Sep 2018 09:19:29 -0600 Message-Id: <20180914151935.9714-1-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This stack adds support for capturing the A6xx GPU state. The A6xx GPU state is comprehensive including registers for the GPU and the GMU, shader caches, context clusters and debugbus state. It isn't as straightforward to capture the state as with previous targets. Some of the state is located behind apertures and other registers have special access rules so the complete state is defined by a hodgepodge of lists and structs which makes the code appear way more complex than it is. Jordan Crouse (6): drm/msm/a6xx: rnndb updates for a6xx drm/msm/a6xx: Fix PDC register overlap drm/msm/a6xx: Rename gmu phandle to qcom,gmu drm/msm/gpu: Move gpu_poll_timeout() to adreno_gpu.h drm/msm/adreno: Don't capture registers if target doesn't need them drm/msm/a6xx: Add a6xx gpu state drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 5 - drivers/gpu/drm/msm/adreno/a6xx.xml.h | 642 ++++++---- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 112 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 9 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 26 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 41 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 6 + drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 1159 +++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 430 +++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 + 12 files changed, 2113 insertions(+), 343 deletions(-) create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h