From patchwork Wed Jun 17 14:51:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 11610023 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 49FA113B1 for ; Wed, 17 Jun 2020 14:51:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3010C208B3 for ; Wed, 17 Jun 2020 14:51:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="h97C+k8y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726835AbgFQOvw (ORCPT ); Wed, 17 Jun 2020 10:51:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725894AbgFQOvv (ORCPT ); Wed, 17 Jun 2020 10:51:51 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F51AC06174E for ; Wed, 17 Jun 2020 07:51:51 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id u128so1375964pgu.13 for ; Wed, 17 Jun 2020 07:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=66urSHPu2efS+32Pqzoys5Raxw2fRk+bGC6RlneeuRo=; b=h97C+k8ylseDAfHw4T4eqkY9Jza6VQnKM4iJxgFLCrg7jw2QLqDoh1WLySycMWJkDq JJjOVXRuBfdHtar8huMK1CiRfo4YVONH/6jpkUzHBJgkYd+HQSYaoLYwk4s7QL+xLy2u evYpk3fE9aQm7AEu0Gm38X9jQSW5Ohilo/dAM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=66urSHPu2efS+32Pqzoys5Raxw2fRk+bGC6RlneeuRo=; b=E0Gs0gi6OgTWedQtwvzhC1EFgFiByfLET2MiXx9uUvIgmJa9ul+1X7iReZ3iyDlKL3 LBpFFvrm16W/xJ6k47MFDDI/eUBtNyYjG3we4hoMKuT0/Dc99rrivrvUDEL5uLlZzdiT /teK5N2glwRPHOZ3YDCgUmvyvLdtjcool/huihjelXQUrQBRYs+oiGohbOlhJWhfv/nH t3ZBBi2el/O2JAhJnoczyFprzWSwsOSsUDUeV6sC+C3oaZlvV3m4JxGfW8k0Xa8PAptj 1AyMLZZKQ2P8kGWkEBC51J/KKDeHJg9jGSxL39WKA8FQrkdKJ+OGppo5fM4gXNxWWlpF +uCg== X-Gm-Message-State: AOAM532FIQhUd+OPQisHZgssxj4TPamMgulIADSjz4RI790tYGF2JP66 R1fI7s6jZOS9a4ft1jVQ1bviJQ== X-Google-Smtp-Source: ABdhPJyKlaYdlG28apy/dV4lrjPIdZ9x/wH0LnJd7AhxvioZHBIrcl/BvGYMi2kMv19lahz9TgaNKQ== X-Received: by 2002:a63:3e09:: with SMTP id l9mr6931881pga.235.1592405510849; Wed, 17 Jun 2020 07:51:50 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id k18sm147040pfp.208.2020.06.17.07.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Jun 2020 07:51:50 -0700 (PDT) From: Douglas Anderson To: Srinivas Kandagatla , Rob Herring , Bjorn Andersson , Andy Gross Cc: dhavalp@codeaurora.org, mturney@codeaurora.org, rnayak@codeaurora.org, Ravi Kumar Bokka , linux-arm-msm@vger.kernel.org, saiprakash.ranjan@codeaurora.org, sparate@codeaurora.org, mkurumel@codeaurora.org, Douglas Anderson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/4] nvmem: qfprom: Patches for fuse blowing on Qualcomm SoCs Date: Wed, 17 Jun 2020 07:51:12 -0700 Message-Id: <20200617145116.247432-1-dianders@chromium.org> X-Mailer: git-send-email 2.27.0.290.gba653c62da-goog MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This series enables blowing of fuses on Qualcomm SoCs by extending the existing qfprom driver with write support. A few notes: - Though I don't have any firsthand knowledge of it, it's my understanding that these changes could be used on any Qualcomm SoC. However, it's likely not very useful on most boards because the bootloader protects against this. Thus the write support here is likely only useful with a cooperating bootloader. - Blowing fuses is truly a one-way process. If you mess around with this and do something wrong you could irreparably brick your chip. You have been warned. Versions 1 and 2 of this series were posted by Ravi Kumar Bokka. I am posting version 3 containing my changes / fixups with his consent. I have left authorship as Ravi but added my own Signed-off-by. Changes in v3: - Split conversion to yaml into separate patch new in v3. - Use 'const' for compatible instead of a 1-entry enum. - Changed filename to match compatible string. - Add #address-cells and #size-cells to list of properties. - Fixed up example. - Add an extra reg range (at 0x6000 offset for SoCs checked) - Define two options for reg: 1 item or 4 items. - No reg-names. - Add "clocks" and "clock-names" to list of properties. - Clock is now "sec", not "secclk". - Add "vcc-supply" to list of properties. - Fixed up example. - Don't provide "reset" value for things; just save/restore. - Use the major/minor version read from 0x6000. - Reading should still read "corrected", not "raw". - Added a sysfs knob to allow you to read "raw" instead of "corrected" - Simplified the SoC data structure. - No need for quite so many levels of abstraction for clocks/regulator. - Don't set regulator voltage. Rely on device tree to make sure it's right. - Properly undo things in the case of failure. - Don't just keep enabling the regulator over and over again. - Enable / disable the clock each time - Polling every 100 us but timing out in 10 us didn't make sense; swap. - No reason for 100 us to be SoC specific. - No need for reg-names. - We shouldn't be creating two separate nvmem devices. - Name is now 'efuse' to match what schema checker wants. - Reorganized ranges to match driver/bindings changes. - Added 4th range as per driver/binding changes. - No more reg-names as per driver/binding changes. - Clock name is now just "sec" as per driver/binding changes. Ravi Kumar Bokka (4): dt-bindings: nvmem: qfprom: Convert to yaml dt-bindings: nvmem: Add properties needed for blowing fuses nvmem: qfprom: Add fuse blowing support arm64: dts: qcom: sc7180: Add properties to qfprom for fuse blowing .../bindings/nvmem/qcom,qfprom.yaml | 86 +++++ .../devicetree/bindings/nvmem/qfprom.txt | 35 -- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 +- drivers/nvmem/qfprom.c | 314 +++++++++++++++++- 5 files changed, 401 insertions(+), 48 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml delete mode 100644 Documentation/devicetree/bindings/nvmem/qfprom.txt