| Message ID | 20220520183114.1356599-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: qcom: Fix higher MSI vectors handling | expand |
On Fri, May 20, 2022 at 09:31:07PM +0300, Dmitry Baryshkov wrote: > I have replied with my Tested-by to the patch at [2], which has landed > in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: > Add support for handling MSIs from 8 endpoints"). However lately I > noticed that during the tests I still had 'pcie_pme=nomsi', so the > device was not forced to use higher MSI vectors. > > After removing this option I noticed that hight MSI vectors are not > delivered on tested platforms. After additional research I stumbled upon > a patch in msm-4.14 ([1]), which describes that each group of MSI > vectors is mapped to the separate interrupt. Implement corresponding > mapping. > > The first patch in the series is a revert of [2] (landed in pci-next). > Either both patches should be applied or both should be dropped. > > Patchseries dependecies: [3] (for the schema change). > > Changes since v10: > - Remove has_split_msi_irqs flag. Trust DT and use split MSI IRQs if > they are described in the DT. This removes the need for the > pcie-qcom.c changes (everything is handled by the core (suggested by > Johan). You could also mention the rebase and fixed warnings with less than eight msi. > [1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22 > [2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@linaro.org/ > [3] https://lore.kernel.org/linux-arm-msm/20220422211002.2012070-1-dmitry.baryshkov@linaro.org/ > > > Dmitry Baryshkov (7): > PCI: dwc: Convert msi_irq to the array > PCI: dwc: split MSI IRQ parsing/allocation to a separate function > PCI: dwc: Handle MSIs routed to multiple GIC interrupts > PCI: dwc: Implement special ISR handler for split MSI IRQ setup > dt-bindings: PCI: qcom: Support additional MSI interrupts > arm64: dts: qcom: sm8250: provide additional MSI interrupts > dt-bindings: mfd: qcom,qca639x: add binding for QCA639x defvice Looks like you used the wrong offsets from HEAD or something when generating the series as the first two patches ([1] above, which is not yet in linux-next, and the dw_pcie_free_msi() fix) are now missing and the last patch is new and unrelated. Johan
On 23/05/2022 10:42, Johan Hovold wrote: > On Fri, May 20, 2022 at 09:31:07PM +0300, Dmitry Baryshkov wrote: >> I have replied with my Tested-by to the patch at [2], which has landed >> in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: >> Add support for handling MSIs from 8 endpoints"). However lately I >> noticed that during the tests I still had 'pcie_pme=nomsi', so the >> device was not forced to use higher MSI vectors. >> >> After removing this option I noticed that hight MSI vectors are not >> delivered on tested platforms. After additional research I stumbled upon >> a patch in msm-4.14 ([1]), which describes that each group of MSI >> vectors is mapped to the separate interrupt. Implement corresponding >> mapping. >> >> The first patch in the series is a revert of [2] (landed in pci-next). >> Either both patches should be applied or both should be dropped. >> >> Patchseries dependecies: [3] (for the schema change). >> >> Changes since v10: >> - Remove has_split_msi_irqs flag. Trust DT and use split MSI IRQs if >> they are described in the DT. This removes the need for the >> pcie-qcom.c changes (everything is handled by the core (suggested by >> Johan). > > You could also mention the rebase and fixed warnings with less than > eight msi. > >> [1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22 >> [2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@linaro.org/ >> [3] https://lore.kernel.org/linux-arm-msm/20220422211002.2012070-1-dmitry.baryshkov@linaro.org/ >> >> >> Dmitry Baryshkov (7): >> PCI: dwc: Convert msi_irq to the array >> PCI: dwc: split MSI IRQ parsing/allocation to a separate function >> PCI: dwc: Handle MSIs routed to multiple GIC interrupts >> PCI: dwc: Implement special ISR handler for split MSI IRQ setup >> dt-bindings: PCI: qcom: Support additional MSI interrupts >> arm64: dts: qcom: sm8250: provide additional MSI interrupts >> dt-bindings: mfd: qcom,qca639x: add binding for QCA639x defvice > > Looks like you used the wrong offsets from HEAD or something when > generating the series as the first two patches ([1] above, which is not > yet in linux-next, and the dw_pcie_free_msi() fix) are now missing and > the last patch is new and unrelated. Ugh. Please excuse me. > > Johan
I have replied with my Tested-by to the patch at [2], which has landed in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints"). However lately I noticed that during the tests I still had 'pcie_pme=nomsi', so the device was not forced to use higher MSI vectors. After removing this option I noticed that hight MSI vectors are not delivered on tested platforms. After additional research I stumbled upon a patch in msm-4.14 ([1]), which describes that each group of MSI vectors is mapped to the separate interrupt. Implement corresponding mapping. The first patch in the series is a revert of [2] (landed in pci-next). Either both patches should be applied or both should be dropped. Patchseries dependecies: [3] (for the schema change). Changes since v10: - Remove has_split_msi_irqs flag. Trust DT and use split MSI IRQs if they are described in the DT. This removes the need for the pcie-qcom.c changes (everything is handled by the core (suggested by Johan). Changes since v9: - Relax requirements and stop validating the DT. If the has_split_msi was specified, parse as many msiN irqs as specified in DT. If there are none, fallback to the single "msi" IRQ. Changes since v8: - Fix typos noted by Bjorn Helgaas - Add missing links to the patch 1 (revert) - Fix sm8250 interrupt-names (Johan) - Specify num_vectors in qcom configuration data (Johan) - Rework parsing of MSI IRQs (Johan) Changes since v7: - Move code back to the dwc core driver (as required by Rob), - Change dt schema to require either a single "msi" interrupt or an array of "msi0", "msi1", ... "msi7" IRQs. Disallow specifying a part of the array (the DT should specify the exact amount of MSI IRQs allowing fallback to a single "msi" IRQ), - Fix in the DWC init code for the dma_mapping_error() return value. Changes since v6: - Fix indentation of the arguments as requested by Stanimir Changes since v5: - Fixed commit subject and in-comment code according to Bjorn's suggestion, - Changed variable idx to i to follow dw_handle_msi_irq() style. Changes since v4: - Fix the minItems/maxItems properties in the YAML schema. Changes since v3: - Reimplement MSI handling scheme in the Qualcomm host controller driver. Changes since v2: - Fix and rephrase commit message for patch 2. Changes since v1: - Split a huge patch into three patches as suggested by Bjorn Helgaas - snps,dw-pcie removal is now part of [3] [1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22 [2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@linaro.org/ [3] https://lore.kernel.org/linux-arm-msm/20220422211002.2012070-1-dmitry.baryshkov@linaro.org/ Dmitry Baryshkov (7): PCI: dwc: Convert msi_irq to the array PCI: dwc: split MSI IRQ parsing/allocation to a separate function PCI: dwc: Handle MSIs routed to multiple GIC interrupts PCI: dwc: Implement special ISR handler for split MSI IRQ setup dt-bindings: PCI: qcom: Support additional MSI interrupts arm64: dts: qcom: sm8250: provide additional MSI interrupts dt-bindings: mfd: qcom,qca639x: add binding for QCA639x defvice .../devicetree/bindings/mfd/qcom,qca639x.yaml | 84 ++++++ .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 +- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 2 +- .../pci/controller/dwc/pcie-designware-host.c | 239 +++++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 10 files changed, 326 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml