From patchwork Tue Jun 21 00:50:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 12888618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1E6AC433EF for ; Tue, 21 Jun 2022 00:50:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233548AbiFUAut (ORCPT ); Mon, 20 Jun 2022 20:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbiFUAus (ORCPT ); Mon, 20 Jun 2022 20:50:48 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C77F6566 for ; Mon, 20 Jun 2022 17:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1655772647; x=1687308647; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=B93LUtgeHI46zztyc8o3DmI5u1tr8jKC+6dUOJ4qO/U=; b=PmrZ5H9REw6IhRW7xxPr/zSzzZBwal052OM8NJoORyNSQEYMni4xF08G 5LYBq26WmGDui933lDwI5L9BwxG2e31tpECktIV6BsWiwdYt9nlyl8p2Z sTOetgGurS2kHkgSxK7k6LXFwdf3QxO2U+HOVkxw1h3VSxVwC/vL3q92G Y=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 Jun 2022 17:50:47 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2022 17:50:46 -0700 Received: from JESSZHAN.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 20 Jun 2022 17:50:46 -0700 From: Jessica Zhang To: CC: Jessica Zhang , , , , , , , , Subject: [PATCH v3 0/4] Expand CRC to support interface blocks Date: Mon, 20 Jun 2022 17:50:30 -0700 Message-ID: <20220621005033.274-1-quic_jesszhan@quicinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Refactor existing CRC code for layer mixer and add CRC support for interface blocks Changes since V1: - Create helper methods for collect_misr and setup_misr in dpu_hw_util.c - Move common bitmasks into dpu_hw_util.h - Update copyrights - Create a dynamically allocated crcs array in dpu_crtc_state - Collect CRCs for all drm_encoders connected to the crtc Changes since V2: - Separate dpu_hw_util changes into a separate patch - Revert back to using a static array and define a macro for MAX_CRC_ENTRIES Jessica Zhang (4): drm/msm/dpu: Move LM CRC code into separate method drm/msm/dpu: Generalize MISR methods to hw_util drm/msm/dpu: Add MISR register support for interface drm/msm/dpu: Add interface support for CRC debugfs drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 130 +++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 11 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 64 ++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 19 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 42 +------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 49 +++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 16 +++ 9 files changed, 287 insertions(+), 74 deletions(-)