From patchwork Sat Sep 24 16:02:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 12987780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F9DAC07E9D for ; Sat, 24 Sep 2022 16:03:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233846AbiIXQDJ (ORCPT ); Sat, 24 Sep 2022 12:03:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232545AbiIXQDI (ORCPT ); Sat, 24 Sep 2022 12:03:08 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB30438697 for ; Sat, 24 Sep 2022 09:03:05 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 10so4654666lfy.5 for ; Sat, 24 Sep 2022 09:03:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=BucyVOTsY93CmgDyVGjJvCDbPEfzNq863eBEEbR0ty8=; b=P8iGfXM7V6D4PZU/Rq9v2t6Wz7Ww4eUzr8f2CGVtC9TxKUOKUDT0Qn+cOXuqKmmfht n/zW35BOL37tMg2mkRNgSHnoWHB/v6CbmVIsH81Cg9+Qt8yku2hzWapyVUu4qaMphlTo x64l7DrN1M8ceHYp4ObS2L297GC4gsAYl13Efa4otrwxpb+t8LL4jYCoQBcJiXKJKd5y G5z98gu7LMcENPuHjkqEUITbkQpJVKm/T2nnJAPi3qjVQzmobadAxUR/Ib+via5ROYM7 gEp8Vb7eoiBi06IEePKCIntawSR7cSTO97DBWesQ4aKyMUziLCwIIXQHO4MNcxDigBIr mFxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=BucyVOTsY93CmgDyVGjJvCDbPEfzNq863eBEEbR0ty8=; b=wnoBT28FfTtyWxMQQqmle7/bNT6yndtvHuq4V9ozViysJFGrIAigBYCxwOF9nYhD0i z/Cgcb13Pat+u+w3r0qSoHhYo0KVztWmjBHq44YhokHrDQX5kAC1E9xFwo13VUT6YtXy txee3jsjkp+2QCrZppRD+wLMv8QCSpvVW4Olm7Wc4cuQCGm57NNf4k9YY2Wgs3r5ugTB +NP0L1FbCpSigT/Kiyn0q1yiLLk1OOX6cOfqNMijieotGsserVvqpLeVpVzFn905o46j 4Vi1Zhr6X1bpM2vUCcyM7gHL/B2qCKuqroe1/nexrj6X/Vk5rMv7G0xAJyS0LgOlEfwu rbNw== X-Gm-Message-State: ACrzQf1jpSXY5PbxU/fJIHjumq1+TCINB1umOIqQwycsjMCm25yQbh6D 4eJo6lJf8kE1Rmvfl0h4t99MDA== X-Google-Smtp-Source: AMsMyM5+juhEb5OjwTdEs+P0qVZDQxw0PADVmXoMvEDJQAeFTGQ7aObsoWWWg7512TTP4B/tU9YgMA== X-Received: by 2002:a05:6512:3f8b:b0:492:d1ed:5587 with SMTP id x11-20020a0565123f8b00b00492d1ed5587mr5801675lfa.355.1664035384150; Sat, 24 Sep 2022 09:03:04 -0700 (PDT) Received: from eriador.lumag.spb.ru ([95.161.222.31]) by smtp.gmail.com with ESMTPSA id 9-20020ac25f09000000b00499f9ba6af0sm1928015lfq.207.2022.09.24.09.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Sep 2022 09:03:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v4 0/6] PCI: qcom: Support using the same PHY for both RC and EP Date: Sat, 24 Sep 2022 19:02:56 +0300 Message-Id: <20220924160302.285875-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Programming of QMP PCIe PHYs slightly differs between RC and EP modes. Currently both qcom and qcom-ep PCIe controllers setup the PHY in the default mode, making it impossible to select at runtime whether the PHY should be running in RC or in EP modes. Usually this is not an issue, since for most devices only the RC mode is used. Some devices (SDX55) currently support only the EP mode without supporting the RC mode (at this moment). Nevertheless some of the Qualcomm platforms (e.g. the aforementioned SDX55) would still benefit from being able to switch between RC and EP depending on the driver being used. While it is possible to use different compat strings for the PHY depending on the mode, it seems like an incorrect approach, since the PHY doesn't differ between usecases. It's the PCIe controller, who should decide how to configure the PHY. This patch series implements the ability to select between RC and EP modes, by allowing the PCIe QMP PHY driver to switch between programming tables. This patchseries depends on the header from the pre-6.1 phy/next. Thus after the 6.1 the PCIe patches can be applied independently of the PHY part. Changes since v3: - Rebased on top of phy/next to pick in newly defined PHY_MODE_PCIE_RC/EP. - Renamed 'main' to 'common' and 'secondary' to 'extra' to reflect the intention of the split (the 'common' tables and the 'extra for the ... mode' tables). - Merged the 'pointer' patch into first and second patches to make them more obvious. Changes since v2: - Added PHY_SUBMODE_PCIE_RC/EP defines (Vinod), - Changed `primary' table name to `main', added extra comments describing that `secondary' are the additional tables, not required in most of the cases (following the suggestion by Johan to rename `primary' table), - Changed secondary tables into the pointers to stop wasting extra memory (Vinod), - Split several functions for programming the PHY using these tables. Changes since v1: - Split the if(table) removal to the separate patch - Expanded commit messages and comments to provide additional details - Fixed build error on pcie-qcom.c - Added support for EP mode on sm8450 to demonstrate the usage of this patchset Changes since RFC: - Fixed the compilation of PCIe EP driver, - Changed pri/sec names to primary and secondary, - Added comments regarding usage of secondary_rc/_ep fields. Dmitry Baryshkov (6): phy: qcom-qmp-pcie: split register tables into common and extra parts phy: qcom-qmp-pcie: split PHY programming to separate functions phy: qcom-qmp-pcie: support separate tables for EP mode phy: qcom-qmp-pcie: Support SM8450 PCIe1 PHY in EP mode PCI: qcom: Setup PHY to work in RC mode PCI: qcom-ep: Setup PHY to work in EP mode drivers/pci/controller/dwc/pcie-qcom-ep.c | 5 + drivers/pci/controller/dwc/pcie-qcom.c | 5 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 298 +++++++++++++----- .../qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 + 4 files changed, 229 insertions(+), 80 deletions(-)