| Message ID | 20221013175712.7539-1-vidyas@nvidia.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: designware-ep: Fix DBI access before core init | expand |
Hi Vidya, On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: > This series attempts to fix the issue with core register (Ex:- DBI) accesses > causing system hang issues in platforms where there is a dependency on the > availability of PCIe Reference clock from the host for their core > initialization. > This series is verified on Tegra194 & Tegra234 platforms. > > Manivannan, could you please verify on qcom platforms? > Currently I'm on paternity leave this week and next. Will test/review the latest version once I'm back. Thanks, Mani > V5: > * Addressed review comments from Bjorn > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() > * Skipped memory allocation if done already. This is to avoid freeing and then > allocating again during PERST# toggles from the host. > > V4: > * Addressed review comments from Bjorn and Manivannan > * Added .ep_init_late() ops > * Added patches to refactor code in qcom and tegra platforms > > Vidya Sagar (3): > PCI: designware-ep: Fix DBI access before core init > PCI: qcom-ep: Refactor EP initialization completion > PCI: tegra194: Refactor EP initialization completion > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 10 +- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- > 4 files changed, 97 insertions(+), 69 deletions(-) > > -- > 2.17.1 >
On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: > This series attempts to fix the issue with core register (Ex:- DBI) accesses > causing system hang issues in platforms where there is a dependency on the > availability of PCIe Reference clock from the host for their core > initialization. > This series is verified on Tegra194 & Tegra234 platforms. > > Manivannan, could you please verify on qcom platforms? > Vidya, any plan to respin this series? The EPC rework series is now merged for v6.3. Thanks, Mani > V5: > * Addressed review comments from Bjorn > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() > * Skipped memory allocation if done already. This is to avoid freeing and then > allocating again during PERST# toggles from the host. > > V4: > * Addressed review comments from Bjorn and Manivannan > * Added .ep_init_late() ops > * Added patches to refactor code in qcom and tegra platforms > > Vidya Sagar (3): > PCI: designware-ep: Fix DBI access before core init > PCI: qcom-ep: Refactor EP initialization completion > PCI: tegra194: Refactor EP initialization completion > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- > drivers/pci/controller/dwc/pcie-designware.h | 10 +- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- > 4 files changed, 97 insertions(+), 69 deletions(-) > > -- > 2.17.1 >
On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote: > External email: Use caution opening links or attachments > > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: >> This series attempts to fix the issue with core register (Ex:- DBI) accesses >> causing system hang issues in platforms where there is a dependency on the >> availability of PCIe Reference clock from the host for their core >> initialization. >> This series is verified on Tegra194 & Tegra234 platforms. >> >> Manivannan, could you please verify on qcom platforms? >> > > Vidya, any plan to respin this series? The EPC rework series is now merged for > v6.3. Yes. I'll send an updated series soon. Currently, I'm observing some regression with linux-next on Tegra platform for endpoint mode. I'll post the patches as soon as that is resolved. Thanks, Vidya Sagar > > Thanks, > Mani > >> V5: >> * Addressed review comments from Bjorn >> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() >> * Skipped memory allocation if done already. This is to avoid freeing and then >> allocating again during PERST# toggles from the host. >> >> V4: >> * Addressed review comments from Bjorn and Manivannan >> * Added .ep_init_late() ops >> * Added patches to refactor code in qcom and tegra platforms >> >> Vidya Sagar (3): >> PCI: designware-ep: Fix DBI access before core init >> PCI: qcom-ep: Refactor EP initialization completion >> PCI: tegra194: Refactor EP initialization completion >> >> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- >> drivers/pci/controller/dwc/pcie-designware.h | 10 +- >> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- >> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- >> 4 files changed, 97 insertions(+), 69 deletions(-) >> >> -- >> 2.17.1 >> > > -- > மணிவண்ணன் சதாசிவம்
On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote: > > > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote: > > External email: Use caution opening links or attachments > > > > > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses > > > causing system hang issues in platforms where there is a dependency on the > > > availability of PCIe Reference clock from the host for their core > > > initialization. > > > This series is verified on Tegra194 & Tegra234 platforms. > > > > > > Manivannan, could you please verify on qcom platforms? > > > > > > > Vidya, any plan to respin this series? The EPC rework series is now merged for > > v6.3. > > Yes. I'll send an updated series soon. > Currently, I'm observing some regression with linux-next on Tegra platform > for endpoint mode. I'll post the patches as soon as that is resolved. > Ping! Thanks, Mani > Thanks, > Vidya Sagar > > > > > Thanks, > > Mani > > > > > V5: > > > * Addressed review comments from Bjorn > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() > > > * Skipped memory allocation if done already. This is to avoid freeing and then > > > allocating again during PERST# toggles from the host. > > > > > > V4: > > > * Addressed review comments from Bjorn and Manivannan > > > * Added .ep_init_late() ops > > > * Added patches to refactor code in qcom and tegra platforms > > > > > > Vidya Sagar (3): > > > PCI: designware-ep: Fix DBI access before core init > > > PCI: qcom-ep: Refactor EP initialization completion > > > PCI: tegra194: Refactor EP initialization completion > > > > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +- > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- > > > 4 files changed, 97 insertions(+), 69 deletions(-) > > > > > > -- > > > 2.17.1 > > > > > > > -- > > மணிவண்ணன் சதாசிவம்
On Tue, Mar 07, 2023 at 08:48:39PM +0530, Manivannan Sadhasivam wrote: > On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote: > > > > > > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote: > > > External email: Use caution opening links or attachments > > > > > > > > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: > > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses > > > > causing system hang issues in platforms where there is a dependency on the > > > > availability of PCIe Reference clock from the host for their core > > > > initialization. > > > > This series is verified on Tegra194 & Tegra234 platforms. > > > > > > > > Manivannan, could you please verify on qcom platforms? > > > > > > > > > > Vidya, any plan to respin this series? The EPC rework series is now merged for > > > v6.3. > > > > Yes. I'll send an updated series soon. > > Currently, I'm observing some regression with linux-next on Tegra platform > > for endpoint mode. I'll post the patches as soon as that is resolved. > > > > Ping! > Ping again. - Mani > Thanks, > Mani > > > Thanks, > > Vidya Sagar > > > > > > > > Thanks, > > > Mani > > > > > > > V5: > > > > * Addressed review comments from Bjorn > > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() > > > > * Skipped memory allocation if done already. This is to avoid freeing and then > > > > allocating again during PERST# toggles from the host. > > > > > > > > V4: > > > > * Addressed review comments from Bjorn and Manivannan > > > > * Added .ep_init_late() ops > > > > * Added patches to refactor code in qcom and tegra platforms > > > > > > > > Vidya Sagar (3): > > > > PCI: designware-ep: Fix DBI access before core init > > > > PCI: qcom-ep: Refactor EP initialization completion > > > > PCI: tegra194: Refactor EP initialization completion > > > > > > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- > > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +- > > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- > > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- > > > > 4 files changed, 97 insertions(+), 69 deletions(-) > > > > > > > > -- > > > > 2.17.1 > > > > > > > > > > -- > > > மணிவண்ணன் சதாசிவம் > > -- > மணிவண்ணன் சதாசிவம்
On Tue, Mar 07, 2023 at 08:48:39PM +0530, Manivannan Sadhasivam wrote: > On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote: > > > > > > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote: > > > External email: Use caution opening links or attachments > > > > > > > > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote: > > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses > > > > causing system hang issues in platforms where there is a dependency on the > > > > availability of PCIe Reference clock from the host for their core > > > > initialization. > > > > This series is verified on Tegra194 & Tegra234 platforms. > > > > > > > > Manivannan, could you please verify on qcom platforms? > > > > > > > > > > Vidya, any plan to respin this series? The EPC rework series is now merged for > > > v6.3. > > > > Yes. I'll send an updated series soon. > > Currently, I'm observing some regression with linux-next on Tegra platform > > for endpoint mode. I'll post the patches as soon as that is resolved. > > > > Ping! > Vidya, are you planning to continue working on this series? If you do not have time, please let me know. - Mani > Thanks, > Mani > > > Thanks, > > Vidya Sagar > > > > > > > > Thanks, > > > Mani > > > > > > > V5: > > > > * Addressed review comments from Bjorn > > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() > > > > * Skipped memory allocation if done already. This is to avoid freeing and then > > > > allocating again during PERST# toggles from the host. > > > > > > > > V4: > > > > * Addressed review comments from Bjorn and Manivannan > > > > * Added .ep_init_late() ops > > > > * Added patches to refactor code in qcom and tegra platforms > > > > > > > > Vidya Sagar (3): > > > > PCI: designware-ep: Fix DBI access before core init > > > > PCI: qcom-ep: Refactor EP initialization completion > > > > PCI: tegra194: Refactor EP initialization completion > > > > > > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- > > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +- > > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- > > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- > > > > 4 files changed, 97 insertions(+), 69 deletions(-) > > > > > > > > -- > > > > 2.17.1 > > > > > > > > > > -- > > > மணிவண்ணன் சதாசிவம் > > -- > மணிவண்ணன் சதாசிவம்