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Thu, 13 Oct 2022 10:57:19 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 10:57:19 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 10:57:14 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V5 0/3] PCI: designware-ep: Fix DBI access before core init Date: Thu, 13 Oct 2022 23:27:09 +0530 Message-ID: <20221013175712.7539-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT016:EE_|CH0PR12MB5297:EE_ X-MS-Office365-Filtering-Correlation-Id: 96c065dd-d0db-49ba-8df6-08daad446b06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 17:57:38.9444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96c065dd-d0db-49ba-8df6-08daad446b06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5297 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This series attempts to fix the issue with core register (Ex:- DBI) accesses causing system hang issues in platforms where there is a dependency on the availability of PCIe Reference clock from the host for their core initialization. This series is verified on Tegra194 & Tegra234 platforms. Manivannan, could you please verify on qcom platforms? V5: * Addressed review comments from Bjorn * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() * Skipped memory allocation if done already. This is to avoid freeing and then allocating again during PERST# toggles from the host. V4: * Addressed review comments from Bjorn and Manivannan * Added .ep_init_late() ops * Added patches to refactor code in qcom and tegra platforms Vidya Sagar (3): PCI: designware-ep: Fix DBI access before core init PCI: qcom-ep: Refactor EP initialization completion PCI: tegra194: Refactor EP initialization completion .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 10 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- 4 files changed, 97 insertions(+), 69 deletions(-)