From patchwork Fri Dec 16 23:07:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 13075597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABD95C46467 for ; Fri, 16 Dec 2022 23:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229843AbiLPXH6 (ORCPT ); Fri, 16 Dec 2022 18:07:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229705AbiLPXHz (ORCPT ); Fri, 16 Dec 2022 18:07:55 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6725654C8; Fri, 16 Dec 2022 15:07:54 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BGMu9Wl022049; Fri, 16 Dec 2022 23:07:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=ZXRlatZE/lijZte1r8U3ti3WvzRijNca0cDjUqcxq3U=; b=Svz/gqLn9etXv03/pvqtrHaUJY6dF6prNLdJto6rCGfFafaHwqsGK44XVFaYDcqdSGEp B+zBwyH737Xj95YTlR63nT1j1Op30zsCCbeid0cdAqsEX5mWBMn5yzpkLSwdhOVNa1yC 4/wsQHZ+LzMhlnyll5iSsWxEUY9VNl5NbVdkzLH0uUhD/h1MXjcHpR6s3uLpOIPpQyJ9 YCdkO2vi2e+ZgoSq/dm/MqAR+Jdm9OGuGDHzDF4K4s6gIddth0+KBDdlwsXE6hhVOVFr KVXs5mwf2SM0Kf2DBFJdiKYjqesaRoeZJRi2XzR87Qu8uQSdFVxjcoQxi7bYMop46z0i Jg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3mg6tew1wa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 23:07:50 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2BGN7mV7004270 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Dec 2022 23:07:48 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 16 Dec 2022 15:07:48 -0800 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Michael Turquette , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski CC: Taniya Das , , , , , Melody Olvera Subject: [PATCH v5 0/2] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs Date: Fri, 16 Dec 2022 15:07:20 -0800 Message-ID: <20221216230722.21404-1-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ucLSL9V_66MimMZkWAeHHTkFkntDO83W X-Proofpoint-GUID: ucLSL9V_66MimMZkWAeHHTkFkntDO83W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-16_14,2022-12-15_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1011 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212160204 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This series adds the GCC, RPMh, and PDC clock support required for the QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit 1000 are new SoCs meant for enabling Open RAN solutions. See more at https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf Changes from v4: - removed syscon from bindings and update style - removed optional clocks and redundant properties - updated compatible to new standard Changes from v3: - added example sources for PCIE and USB clocks - added index enum in GCC clock driver - fixed some style issues - removed pdc patches from set Changes from v2: - Revised dt-bindings - Removed qru compat strings - Updated some clocks to use clk_branch ops instead of clk_branch2 and HALT_ENABLE Melody Olvera (1): dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocks Taniya Das (1): clk: qcom: Add QDU1000 and QRU1000 GCC support .../bindings/clock/qcom,qdu1000-gcc.yaml | 51 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-qdu1000.c | 2653 +++++++++++++++++ include/dt-bindings/clock/qcom,qdu1000-gcc.h | 175 ++ 5 files changed, 2888 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml create mode 100644 drivers/clk/qcom/gcc-qdu1000.c create mode 100644 include/dt-bindings/clock/qcom,qdu1000-gcc.h base-commit: ca39c4daa6f7f770b1329ffb46f1e4a6bcc3f291