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[71.184.142.128]) by smtp.gmail.com with ESMTPSA id j3-20020a05620a288300b006f9c2be0b4bsm7217436qkp.135.2022.12.19.11.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 11:11:59 -0800 (PST) From: Eric Chanudet To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Halaney , Brian Masney , Eric Chanudet Subject: [PATCH v4 0/4] arm64: dts: qcom: enable sa8540p-ride rtc Date: Mon, 19 Dec 2022 14:09:57 -0500 Message-Id: <20221219191000.2570545-1-echanude@redhat.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable sa8540p-ride rtc on pmic@0. sa8540p base boards share the same pmics description, currently in pm8450a.dtsi. Rename the file to make this explicit and use it in both sa8540p-ride.dts and sa8295p-adp.dts. Add the missing offset where appropriate for the alarm register bank in other qcom,pm8941-rtc description. Changes since v3: - Amend patch #1 incorrect description. Changes since v2: - rename pm8450a.dtsi to sa8540p-pmics.dtsi. Changes since v1: - Add "alarm" register bank offset at 0x6100 in qcom,pm8941-rtc descriptions. Eric Chanudet (4): arm64: dts: qcom: rename pm8450a dtsi to sa8540p-pmics arm64: dts: qcom: sa8450p-pmics: add rtc node arm64: dts: qcom: sa8295p-adp: use sa8540p-pmics arm64: dts: qcom: pm8941-rtc add alarm register arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm8916.dtsi | 3 +- arch/arm64/boot/dts/qcom/pm8950.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/pms405.dtsi | 2 +- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 79 +------------------ .../qcom/{pm8450a.dtsi => sa8540p-pmics.dtsi} | 8 ++ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 +- 9 files changed, 17 insertions(+), 85 deletions(-) rename arch/arm64/boot/dts/qcom/{pm8450a.dtsi => sa8540p-pmics.dtsi} (90%) Tested-by: Andrew Halaney # sa8540p-ride