| Message ID | 20230208091340.124641-1-konrad.dybcio@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | SM6(11|12|37)5 GPUCC | expand |
On 8.02.2023 10:13, Konrad Dybcio wrote: > This series brings GPUCC support and the correlated bindings for > three midrange SoCs, all of which host a GMU-less A6xx GPU. > ping! Konrad > v6 includes bitfield.h for arm32 builds and fixes the kconfig display name (6115 != 6125, heh) in [10/10] > > v5: https://lore.kernel.org/linux-arm-msm/20230201183626.351211-1-konrad.dybcio@linaro.org/ > > v5 fixes some issues pointed out by Dmitry and picks up tags > > v4: https://lore.kernel.org/linux-arm-msm/20230130235926.2419776-1-konrad.dybcio@linaro.org/ > > v4 only brings a tiny bindings amend to [7/8].. I thought I could > fix it without running dt_binding_check but oh was I humbled again.. > > v3: https://lore.kernel.org/linux-arm-msm/20230130153252.2310882-1-konrad.dybcio@linaro.org/T/#t > > Konrad Dybcio (10): > clk: qcom: branch: Add helper functions for setting retain bits > clk: qcom: branch: Add helper functions for setting SLEEP/WAKE bits > clk: qcom: branch: Move CBCR bits definitions to the header file > clk: qcom: branch: Clean up branch enable registers > dt-bindings: clock: Add Qcom SM6125 GPUCC > clk: qcom: Add GPU clock controller driver for SM6125 > dt-bindings: clock: Add Qcom SM6375 GPUCC > clk: qcom: Add GPU clock controller driver for SM6375 > dt-bindings: clock: Add Qcom SM6115 GPUCC > clk: qcom: Add GPU clock controller driver for SM6115 > > .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 ++ > .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++ > .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++ > drivers/clk/qcom/Kconfig | 27 + > drivers/clk/qcom/Makefile | 3 + > drivers/clk/qcom/clk-branch.c | 15 +- > drivers/clk/qcom/clk-branch.h | 44 ++ > drivers/clk/qcom/gpucc-sm6115.c | 503 ++++++++++++++++++ > drivers/clk/qcom/gpucc-sm6125.c | 424 +++++++++++++++ > drivers/clk/qcom/gpucc-sm6375.c | 469 ++++++++++++++++ > include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++ > include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 ++ > include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 ++ > 13 files changed, 1760 insertions(+), 10 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml > create mode 100644 drivers/clk/qcom/gpucc-sm6115.c > create mode 100644 drivers/clk/qcom/gpucc-sm6125.c > create mode 100644 drivers/clk/qcom/gpucc-sm6375.c > create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h > create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h > create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h >
On Wed, 8 Feb 2023 10:13:30 +0100, Konrad Dybcio wrote: > This series brings GPUCC support and the correlated bindings for > three midrange SoCs, all of which host a GMU-less A6xx GPU. > > v6 includes bitfield.h for arm32 builds and fixes the kconfig display name (6115 != 6125, heh) in [10/10] > > v5: https://lore.kernel.org/linux-arm-msm/20230201183626.351211-1-konrad.dybcio@linaro.org/ > > [...] Applied, thanks! [01/10] clk: qcom: branch: Add helper functions for setting retain bits commit: b594e6f6605311785171b8d4600fe96e35625530 [02/10] clk: qcom: branch: Add helper functions for setting SLEEP/WAKE bits commit: 0932e565ba7c828d5ec59f872cb3ad6b070dc003 [03/10] clk: qcom: branch: Move CBCR bits definitions to the header file commit: 5ab6561da990375b0a3cd54e12996498f6398a0f [04/10] clk: qcom: branch: Clean up branch enable registers commit: b96fbb03fbc1686449e28e2edb54df5c3584ad43 [06/10] clk: qcom: Add GPU clock controller driver for SM6125 commit: a6b18286810cc64419a36e3a6b5d7191f1f9b167 [08/10] clk: qcom: Add GPU clock controller driver for SM6375 commit: 8397e24278b3690b830e5dad79169a79f63b0b43 [10/10] clk: qcom: Add GPU clock controller driver for SM6115 commit: 092209f199b8fe3e7862aff2d6e45ffb388fc42a Best regards,