From patchwork Thu Mar 9 10:37:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13167189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CB56C6FD1C for ; Thu, 9 Mar 2023 10:38:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbjCIKiC (ORCPT ); Thu, 9 Mar 2023 05:38:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229580AbjCIKiB (ORCPT ); Thu, 9 Mar 2023 05:38:01 -0500 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 567984C1F for ; Thu, 9 Mar 2023 02:37:57 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id bw19so1336822wrb.13 for ; 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Thu, 09 Mar 2023 02:37:55 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:f14c:2275:50fc:c056]) by smtp.gmail.com with ESMTPSA id f2-20020a5d58e2000000b002c56af32e8csm17638119wrd.35.2023.03.09.02.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 02:37:55 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 0/9] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Date: Thu, 9 Mar 2023 11:37:43 +0100 Message-Id: <20230309103752.173541-1-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bartosz Golaszewski This enables the QUPv3 interfaces that are exposed on the sa8775p-ride board: I2C, SPI and the Bluetooth and GNSS UART ports. v4 -> v5: - remove board-specific interrupt from UART17 in SoC dtsi - rearrange node properties to have various *-cells properties come right before status - collect more tags v3 -> v4: - use interconnect constants instead of magic numbers where applicable - pad addresses in reg to 8 digits - group pins under state nodes for UART v2 -> v3: - fix the interrupt number for uart12 - replace underscores with hyphens in DT node names (although make dtbs_check does not raise warnings about this) - rearrange the commits so that they're more fine-grained with separate patches for adding nodes to dtsi and enabling them for the board v1 -> v2: - uart17 is the Bluetooth port, not GNSS - add uart12 for GNSS too in that case Bartosz Golaszewski (9): arm64: dts: qcom: sa8775p: add the QUPv3 #2 node arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2 arm64: dts: qcom: sa8775p: add the i2c18 node arm64: dts: qcom: sa8775p-ride: enable i2c18 arm64: dts: qcom: sa8775p: add the spi16 node arm64: dts: qcom: sa8775p-ride: enable the SPI node arm64: dts: qcom: sa8775p: add high-speed UART nodes arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port arm64: dts: qcom: sa8775p-ride: enable the BT UART port arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 99 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 86 ++++++++++++++++++++ 2 files changed, 185 insertions(+)