mbox series

[V10,0/4] Add minimal boot support for IPQ9574

Message ID 20230327132718.573-1-quic_devipriy@quicinc.com (mailing list archive)
Headers show
Series Add minimal boot support for IPQ9574 | expand

Message

Devi Priya March 27, 2023, 1:27 p.m. UTC 
The IPQ9574 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points

This series adds minimal board boot support for ipq9574-rdp433 variant

V9 can be found at:
https://lore.kernel.org/linux-arm-kernel/20230316072940.29137-1-quic_devipriy@quicinc.com/

Changes in V10:
	- Dropped the pinctrl driver and its binding as it is
	  already part of the linux-next/master
	- Detailed change log is present in the respective patches

Devi Priya (4):
  dt-bindings: clock: Add ipq9574 clock and reset definitions
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  arm64: dts: qcom: Add support for ipq9574 SoC and RDP433 variant
  arm64: defconfig: Enable IPQ9574 SoC base configs

 .../bindings/clock/qcom,ipq9574-gcc.yaml      |   62 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts   |   84 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  270 ++
 arch/arm64/configs/defconfig                  |    2 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/gcc-ipq9574.c                | 4248 +++++++++++++++++
 include/dt-bindings/clock/qcom,ipq9574-gcc.h  |  213 +
 include/dt-bindings/reset/qcom,ipq9574-gcc.h  |  164 +
 10 files changed, 5053 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
 create mode 100644 include/dt-bindings/clock/qcom,ipq9574-gcc.h
 create mode 100644 include/dt-bindings/reset/qcom,ipq9574-gcc.h


base-commit: 011eb7443621f49ca1e8cdf9c74c215f25019118

Comments

Stephen Boyd March 27, 2023, 4:48 p.m. UTC | #1 
Quoting Devi Priya (2023-03-27 06:27:16)
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> new file mode 100644
> index 000000000000..b2a2d618a5ec
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -0,0 +1,4248 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>

What is this include for?

> +#include <linux/regmap.h>

Need to include clk-provider.h

> +
> +#include <linux/reset-controller.h>

Put a newline here.

> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "clk-regmap-phy-mux.h"
> +#include "reset.h"
> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> +       DT_XO,
> +       DT_SLEEP_CLK,
> +       DT_BIAS_PLL_UBI_NC_CLK,
> +       DT_PCIE30_PHY0_PIPE_CLK,
> +       DT_PCIE30_PHY1_PIPE_CLK,
> +       DT_PCIE30_PHY2_PIPE_CLK,
> +       DT_PCIE30_PHY3_PIPE_CLK,
> +       DT_USB3PHY_0_CC_PIPE_CLK,
> +};
> +
> +enum {
> +       P_XO,
> +       P_PCIE30_PHY0_PIPE,
> +       P_PCIE30_PHY1_PIPE,
> +       P_PCIE30_PHY2_PIPE,
> +       P_PCIE30_PHY3_PIPE,
> +       P_USB3PHY_0_PIPE,
> +       P_GPLL0,
> +       P_GPLL0_DIV2,
> +       P_GPLL0_OUT_AUX,
> +       P_GPLL2,
> +       P_GPLL4,
> +       P_PI_SLEEP,
> +       P_BIAS_PLL_UBI_NC_CLK,
> +};
> +
> +static const struct parent_map gcc_xo_map[] = {
> +       { P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_data[] = {
> +       { .index = DT_XO },
> +};
> +
> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
> +       { .index = DT_SLEEP_CLK },
> +};
> +
> +static struct clk_alpha_pll gpll0_main = {
> +       .offset = 0x20000,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +       .clkr = {
> +               .enable_reg = 0x0b000,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data) {

All these clk_init_data structs should be const.

> +                       .name = "gpll0_main",
> +                       .parent_data = gcc_xo_data,
> +                       .num_parents = ARRAY_SIZE(gcc_xo_data),
> +                       .ops = &clk_alpha_pll_ops,
> +               },
> +       },
> +};
Devi Priya March 28, 2023, 6:15 a.m. UTC | #2 
On 3/27/2023 10:18 PM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-03-27 06:27:16)
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>> new file mode 100644
>> index 000000000000..b2a2d618a5ec
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -0,0 +1,4248 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +/*
>> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
> 
> What is this include for?
This include actually don't seem necessary. But, I see that of.h & 
platform_device.h are being included via of_device.h
Would you suggest to drop of_device.h or the other two
headers instead?
> 
>> +#include <linux/regmap.h>
> 
> Need to include clk-provider.h
> 
>> +
>> +#include <linux/reset-controller.h>
> 
> Put a newline here.
Okay
> 
>> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
>> +
>> +#include "clk-rcg.h"
>> +#include "clk-branch.h"
>> +#include "clk-alpha-pll.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "clk-regmap-phy-mux.h"
>> +#include "reset.h"
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> +       DT_XO,
>> +       DT_SLEEP_CLK,
>> +       DT_BIAS_PLL_UBI_NC_CLK,
>> +       DT_PCIE30_PHY0_PIPE_CLK,
>> +       DT_PCIE30_PHY1_PIPE_CLK,
>> +       DT_PCIE30_PHY2_PIPE_CLK,
>> +       DT_PCIE30_PHY3_PIPE_CLK,
>> +       DT_USB3PHY_0_CC_PIPE_CLK,
>> +};
>> +
>> +enum {
>> +       P_XO,
>> +       P_PCIE30_PHY0_PIPE,
>> +       P_PCIE30_PHY1_PIPE,
>> +       P_PCIE30_PHY2_PIPE,
>> +       P_PCIE30_PHY3_PIPE,
>> +       P_USB3PHY_0_PIPE,
>> +       P_GPLL0,
>> +       P_GPLL0_DIV2,
>> +       P_GPLL0_OUT_AUX,
>> +       P_GPLL2,
>> +       P_GPLL4,
>> +       P_PI_SLEEP,
>> +       P_BIAS_PLL_UBI_NC_CLK,
>> +};
>> +
>> +static const struct parent_map gcc_xo_map[] = {
>> +       { P_XO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_data[] = {
>> +       { .index = DT_XO },
>> +};
>> +
>> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
>> +       { .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> +       .offset = 0x20000,
>> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +       .clkr = {
>> +               .enable_reg = 0x0b000,
>> +               .enable_mask = BIT(0),
>> +               .hw.init = &(struct clk_init_data) {
> 
> All these clk_init_data structs should be const.
Okay
> 
>> +                       .name = "gpll0_main",
>> +                       .parent_data = gcc_xo_data,
>> +                       .num_parents = ARRAY_SIZE(gcc_xo_data),
>> +                       .ops = &clk_alpha_pll_ops,
>> +               },
>> +       },
>> +};
Thanks,
Devi Priya
Stephen Boyd March 28, 2023, 4:59 p.m. UTC | #3 
Quoting Devi Priya (2023-03-27 23:15:35)
> 
> 
> On 3/27/2023 10:18 PM, Stephen Boyd wrote:
> > Quoting Devi Priya (2023-03-27 06:27:16)
> >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> >> new file mode 100644
> >> index 000000000000..b2a2d618a5ec
> >> --- /dev/null
> >> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> >> @@ -0,0 +1,4248 @@
> >> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +/*
> >> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
> >> + */
> >> +
> >> +#include <linux/kernel.h>
> >> +#include <linux/err.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_device.h>
> > 
> > What is this include for?
> This include actually don't seem necessary. But, I see that of.h & 
> platform_device.h are being included via of_device.h
> Would you suggest to drop of_device.h or the other two
> headers instead?

Include headers for things you use. Don't try to omit includes if you
see that a header includes other headers that you're using.
Devi Priya March 30, 2023, 9:17 a.m. UTC | #4 
On 3/28/2023 10:29 PM, Stephen Boyd wrote:
> Quoting Devi Priya (2023-03-27 23:15:35)
>>
>>
>> On 3/27/2023 10:18 PM, Stephen Boyd wrote:
>>> Quoting Devi Priya (2023-03-27 06:27:16)
>>>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>>>> new file mode 100644
>>>> index 000000000000..b2a2d618a5ec
>>>> --- /dev/null
>>>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>>>> @@ -0,0 +1,4248 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +/*
>>>> + * Copyright (c) 2023 The Linux Foundation. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/err.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/of.h>
>>>> +#include <linux/of_device.h>
>>>
>>> What is this include for?
>> This include actually don't seem necessary. But, I see that of.h &
>> platform_device.h are being included via of_device.h
>> Would you suggest to drop of_device.h or the other two
>> headers instead?
> 
> Include headers for things you use. Don't try to omit includes if you
> see that a header includes other headers that you're using.
Sure, got it!

Regards,
Devi Priya