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Tue, 19 Mar 2024 03:44:40 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id a5-20020a5d4d45000000b0033e03a6b1ecsm12029459wru.18.2024.03.19.03.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:44:40 -0700 (PDT) From: Neil Armstrong Subject: [PATCH 0/7] arm64: qcom-sm8[456]50: properly describe the PCIe Gen4x2 PHY AUX clock Date: Tue, 19 Mar 2024 11:44:26 +0100 Message-Id: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAIps+WUC/x3NTQ6CMBBA4auQWTtJy694FeKitoNMFJh0wNQQ7 m7j8tu8d4BSZFK4FQdE+rDyumTYSwF+csuTkEM2lKasTWV73FZhjzpfU2NwF90iuRnFM6FFmb7 o9oT+/cL6UTW27TvThQA5J5FGTv/VcD/PH5284G16AAAA To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock named "PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which is muxed & gated then returned to the PHY as an input. Document the clock IDs to select the PIPE clock or the AUX clock, also enforce a second clock-output-names and a #clock-cells value of 1 for the PCIe Gen4x2 PHY found in the SM8[456]50 SoCs. The PHY driver needs a light refactoring to support a second clock, and finally the DT is changed to connect the PHY second clock to the corresponding GCC input then drop the dummy fixed rate clock. Signed-off-by: Neil Armstrong --- Neil Armstrong (7): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs phy: qcom: qmp-pcie: refactor clock register code phy: qcom: qmp-pcie: register second optional PHY AUX clock phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk arm64: dts: qcom: sm8650: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 +- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 - arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 - arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 -- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 - arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 - arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +-- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 104 ++++++++++++++++++--- include/dt-bindings/phy/phy-qcom-qmp.h | 4 + 11 files changed, 129 insertions(+), 64 deletions(-) --- base-commit: 2e93f143ca010a5013528e1cfdc895f024fe8c21 change-id: 20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-4b35169707dd Best regards,