From patchwork Mon Mar 25 10:20:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13601893 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6889224DB; Mon, 25 Mar 2024 10:21:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711362064; cv=none; b=eYXrBFauFp3MkQPF0qDceQSnHcCPysLGIfjV3OuNCEIDzIx+4wtYin/y6cJ8eFP/5lhEShafWbzSp+R4UO7ArHT4K7hDLUxsx67ju8Y4a6I6hwGTAOtNyzkpzwqlrzjw5UXbWyS5okX53K0zCgIlN5rT5kwUiTCUvladbnRbJec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711362064; c=relaxed/simple; bh=fcnh9KN2bWNwKxwz0u8fBtorPz/wfJtgWjD0gXneYto=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=OSJMJMCVPeWgNhd7jzfwwHCP1qoH2eVDkvC0WINim9FQ8HOT0gnksHuQPaVoIZxpafaBWj1x7FVahEwcPYu6hBjkHP7+BGfFQmqMeNXCz0sXHQ+92Mi7LaYWuWuFP7uspstm437rJgeK+w6BzrEprkLepyHJNjpDhF5W7qaUwoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=BX+gcc2Z; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BX+gcc2Z" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42P9TTFd019743; Mon, 25 Mar 2024 10:20:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=IcffQD5 r/DCrkWeuEoMCS5WgcaSsE7f+GLTUFJRqYog=; b=BX+gcc2ZxDLZ1lJ6qKK9u1M oYXXjd0vyyjvaANhdsZiNKfsPuVhJAMnGknLDAH3Z7fnpjii1AboPm3U/KZGxvnX GZuR5gSYA17Rso/9/aj8h3Cs61wtRgMp/fX63cSvM/Pa1VtATZzUKv7dRPDPsBFT qLjh7FlsjZvHDOb6Ivy4HVtjo9jFKLZ/OqtYKLScx0SWDTVJmzbNbtPHoZd5dWZ9 VWwpQQz10dxifi8CJCrlQBkSRuTJVFw/WzRr3agzJOh6MyFCMv4ZKtQuYmxVUdpX F6A7rOXm7xav6G9CnQrLN+cwcWfa9y+wYKKoZHUr1dUjefC6pXw1pHjpqUpVc1A= = Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x2yrurwdn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 10:20:57 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42PAKuYx030905 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 10:20:56 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 03:20:51 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v2 0/4] Add interconnect driver for IPQ9574 SoC Date: Mon, 25 Mar 2024 15:50:32 +0530 Message-ID: <20240325102036.95484-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: A7_2uxPqxX1NkPPuf_jbPdHk9eI1Olpn X-Proofpoint-GUID: A7_2uxPqxX1NkPPuf_jbPdHk9eI1Olpn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-25_08,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403250057 MSM platforms manage NoC related clocks and scaling from RPM. However, in IPQ SoCs, RPM is not involved in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for the accessing the peripherals present in the system. Hence add a minimalistic interconnect driver that establishes a path from the processor/memory to those peripherals and vice versa. --- v2: qcom,ipq9574.h Fix license identifier Rename macros qcom,ipq9574-gcc.yaml Include interconnect-cells gcc-ipq9574.c Update commit log Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig ipq9574.dtsi Moved to separate patch Include interconnect-cells to clock controller node drivers/clk/qcom/Kconfig: Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK Varadarajan Narayanan (4): dt-bindings: clock: Add interconnect-cells dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: add IPQ9574 interconnect clocks support arm64: dts: qcom: ipq9574: Add icc provider ability to gcc .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 + drivers/clk/qcom/Kconfig | 2 + drivers/clk/qcom/gcc-ipq9574.c | 65 ++++++++++++++++++- .../dt-bindings/interconnect/qcom,ipq9574.h | 62 ++++++++++++++++++ 5 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h