From patchwork Tue Apr 2 10:34:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13613673 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AA945FDD2; Tue, 2 Apr 2024 10:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712054074; cv=none; b=apAJ19+G+xkoTpUKtJ92PfaCiWqIAY440dujGiQdV75xwPDrtrqnjH5JhAyKVsIcpjstdlRvURiXrAgiAZ229q/Vq4RHHXqpVfySuxPUJ+IUSwtkNw1OeE03lseBMlOPtfhhkrYA4g9NSN0M3/yBCIrhXGMphSvK0h+YmXQfgDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712054074; c=relaxed/simple; bh=nvPbIMQta9inNL69UqwPZJB/9wmSdGd+rz0uwsafhOo=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Z1wqpfB2zyr1so4Saalct+NYGBRwesAoHqPLxGViYc17PuGlAB5BRKMBtHJLx5v5j5sr7CfiAivNAw5oVfceBxaZMOYm7f6qcs5u5luIuDVWonz0z5B3Wy8JOj+PknlvR4L4wck1x/qdWG+C1QEcMeW8v4baKSxlptoC8yXa5Us= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=pPIUvV6Q; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="pPIUvV6Q" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4327SO7V030590; Tue, 2 Apr 2024 10:34:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=qcppdkim1; bh=GfC8GfN W4k6MjCi7WKh9ZhxXE8ireQ9ETjfjeKbm/N0=; b=pPIUvV6Qq/TqjVXYSRSTi5Z 1cALeTNoxIDaWmyTLNom7X90AtvgMAfChY0C5FT9wGBskSet6UP34n7QRoAGnpDh D3auhilxzv/fLsttYdewe0vtvzGJWe0sTSbJC8rb+YzlB0Aq8Obmw+yFyEvmWkpb h0JKLYD3zoK4/V8G3OZAY620+Vrs6VJhL1Zp+4D+u9czeeZ7nLn36BXkwYNWg72G zBWedaylAEngEqGDgPNzTLSDIs5drC3Q6HyipUd+LxiA45hyEbzo2XeF75kTym88 F36691wPXSxAAf19Wy8XA8SIgky5nL/SKvV8rNJ+ES6nD8CeHSiuoRXV88vNJoA= = Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x893ts0nb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 02 Apr 2024 10:34:26 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 432AYPAR012861 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 Apr 2024 10:34:25 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:20 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v6 0/6] Add interconnect driver for IPQ9574 SoC Date: Tue, 2 Apr 2024 16:04:00 +0530 Message-ID: <20240402103406.3638821-1-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -zuBf1M0eqNHfPb-pUr_JfO7rtzJqSP5 X-Proofpoint-ORIG-GUID: -zuBf1M0eqNHfPb-pUr_JfO7rtzJqSP5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 MSM platforms manage NoC related clocks and scaling from RPM. However, in IPQ SoCs, RPM is not involved in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for the accessing the peripherals present in the system. Hence add a minimalistic interconnect driver that establishes a path from the processor/memory to those peripherals and vice versa. --- v6: Removed 'Reviewed-by: Krzysztof' from dt-bindings patch Remove clock get from ICC driver as suggested by Stephen Boyd so that the actual peripheral can do the clock get first_id -> icc_first_node_id Remove tristate from INTERCONNECT_CLK v5: Split gcc-ipq9574.c and common.c changes into separate patches Introduce devm_icc_clk_register Fix error handling v4: gcc-ipq9574.c Use clk_hw instead of indices common.c Do icc register in qcom_cc_probe() call stream common.h Add icc clock info to qcom_cc_desc structure v3: qcom,ipq9574.h Move 'first id' define to clock driver gcc-ipq9574.c: Use indexed identifiers here to avoid confusion Fix error messages and move code to common.c as it can be shared with future SoCs v2: qcom,ipq9574.h Fix license identifier Rename macros qcom,ipq9574-gcc.yaml Include interconnect-cells gcc-ipq9574.c Update commit log Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig ipq9574.dtsi Moved to separate patch Include interconnect-cells to clock controller node drivers/clk/qcom/Kconfig: Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK Varadarajan Narayanan (6): dt-bindings: interconnect: Add Qualcomm IPQ9574 support interconnect: icc-clk: Remove tristate from INTERCONNECT_CLK interconnect: icc-clk: Add devm_icc_clk_register clk: qcom: common: Add interconnect clocks support clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks arm64: dts: qcom: ipq9574: Add icc provider ability to gcc .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 + drivers/clk/qcom/Kconfig | 2 + drivers/clk/qcom/common.c | 38 ++++++++++++++++++- drivers/clk/qcom/common.h | 3 ++ drivers/clk/qcom/gcc-ipq9574.c | 30 +++++++++++++++ drivers/interconnect/Kconfig | 1 - drivers/interconnect/icc-clk.c | 29 ++++++++++++++ .../dt-bindings/interconnect/qcom,ipq9574.h | 36 ++++++++++++++++++ include/linux/interconnect-clk.h | 4 ++ 10 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h