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Thu, 16 May 2024 03:24:37 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 44G3ObFV032144; Thu, 16 May 2024 03:24:37 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-devipriy-blr.qualcomm.com [10.131.37.37]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 44G3Ob2Z032139 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 03:24:37 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 4059087) id 5F37440FFA; Thu, 16 May 2024 08:54:36 +0530 (+0530) From: devi priya To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, quic_msarkar@quicinc.com, quic_qianyu@quicinc.com, abel.vesa@linaro.org, quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_devipriy@quicinc.com Subject: [PATCH V4 0/4] Add support for PCIe PHY in IPQ9574 Date: Thu, 16 May 2024 08:54:32 +0530 Message-Id: <20240516032436.2681828-1-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0Zj5QkA27A3XAlUHNdfbmkKgo5QvYtHq X-Proofpoint-ORIG-GUID: 0Zj5QkA27A3XAlUHNdfbmkKgo5QvYtHq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_01,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 mlxlogscore=868 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 adultscore=0 mlxscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405160022 This series adds support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. [V4] Picked up the R-b/A-b tags. Split the phy driver and headers to individual patches. [V3] https://lore.kernel.org/linux-arm-msm/20240512082541.1805335-1-quic_devipriy@quicinc.com/ [V2] https://lore.kernel.org/linux-arm-msm/20230519085723.15601-1-quic_devipriy@quicinc.com/ [V1] https://lore.kernel.org/linux-arm-msm/20230421124150.21190-1-quic_devipriy@quicinc.com/ devi priya (4): dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ9574 QMP PCIe PHYs phy: qcom-qmp: Add missing offsets for Qserdes PLL registers. phy: qcom-qmp: Add missing register definitions for PCS V5 phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 2 + drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 309 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 + .../phy/qualcomm/phy-qcom-qmp-qserdes-pll.h | 3 + 4 files changed, 328 insertions(+)