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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d3042fd72sm6323136a12.48.2024.06.25.11.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 11:28:13 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v4 0/5] Add SMEM-based speedbin matching Date: Tue, 25 Jun 2024 20:28:05 +0200 Message-Id: <20240625-topic-smem_speedbin-v4-0-f6f8493ab814@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIADUMe2YC/22NQQqDMBREryJ/3ZQkaJGueo8ixSSjfqiJJBJax Ls3Fbors3oD82ajhMhIdK02isicOPgC9akiO/V+hGBXmLTUtSwRa1jYijRjfqQFcIa9aB1gnTQ YJKgsl4iBX4f13hWeOK0hvo+TrL7tz9f89WUlpLDQpr3UulFG3Z7s+xjOIY7U7fv+AdJ3CbG3A AAA To: Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Daniel Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719340091; l=2579; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=q0yzDllR7onfBxBeyrsV8zllafTESKitM/Jyq0s9Emo=; b=JpscgSq2npI58xUw7s5ODs4eaHFpU60RrwK7wt+iCLtnc4alqW1yzeSbp4IicnuHW33OHT9cx TdPQeojNOYjAao4bhOjQLWkZE7s4MEyzgVdw6s2U2WYiI+bU0eEJuie X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore, but instead rely on a set of combinations of "feature code" (FC) and "product code" (PC) identifiers to match the bins. This series adds support for that. I suppose a qcom/for-soc immutable branch would be in order if we want to land this in the upcoming cycle. FWIW I preferred the fuses myself.. Signed-off-by: Konrad Dybcio --- Changes in v4: - Drop applied qcom patches - Make the fuse/speedbin fields u16 again (as Pcode is unused) - Add comments explaining why there's only speedbin0 for 8550 - Fix some checkpatch fluff (code style) - Rebase on next-20240625 Changes in v3: - Wrap the argument usage in new preprocessor macros in braces (Bjorn) - Make the SOCINFO_FC_INT_MAX define inclusive, adjust .h and .c (Bjorn) - Pick up rbs - Rebase on next-20240605 - Drop the already-applied ("Avoid a nullptr dereference when speedbin setting fails") Changes in v2: - Separate moving existing and adding new defines - Fix kerneldoc copypasta - Remove some wrong comments and defines - Remove assumed "max" values for PCs and external FCs - Improve some commit messages - Return -EOPNOTSUPP instead of -EINVAL when calling p/fcode getters on socinfo older than v16 - Drop pcode getters and evaluation (doesn't matter for Adreno on non-proto SoCs) - Rework the speedbin logic to be hopefully saner - Link to v1: https://lore.kernel.org/r/20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org --- Konrad Dybcio (5): drm/msm/adreno: Implement SMEM-based speed bin drm/msm/adreno: Add speedbin data for SM8550 / A740 drm/msm/adreno: Define A530 speed bins explicitly drm/msm/adreno: Redo the speedbin assignment arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 +++++++- drivers/gpu/drm/msm/adreno/a5xx_catalog.c | 6 +++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 ------------ drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 54 ------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 84 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++- 8 files changed, 118 insertions(+), 97 deletions(-) --- base-commit: 0fc4bfab2cd45f9acb86c4f04b5191e114e901ed change-id: 20240404-topic-smem_speedbin-8deecd0bef0e Best regards,