| Message ID | 20240626-qps615-v1-0-2ade7bd91e02@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: enable Power and configure the QPS615 PCIe switch | expand |
On Wed, 26 Jun 2024 18:07:48 +0530, Krishna chaitanya chundru wrote: > QPS615 is the PCIe switch which has one upstream and three downstream > ports. One of the downstream ports is used as endpoint device of Ethernet > MAC. Other two downstream ports are supposed to connect to external > device. One Host can connect to QPS615 by upstream port. > > QPS615 switch power is controlled by the GPIO's. After powering on > the switch will immediately participate in the link training. if the > host is also ready by that time PCIe link will established. > > The QPS615 needs to configured certain parameters like de-emphasis, > disable unused port etc before link is established. These settings > vary from platform to platform. > > As the controller starts link training before the probe of pwrctl driver, > the PCIe link may come up before configuring the switch itself. > To avoid this introduce two functions in pci_ops to start_link() & > stop_link() which will disable the link training if the PCIe link is > not up yet. > > Now PCI pwrctl device is the child of the pci-pcie bridge, if we want > to enable the suspend resume for pwrctl device there may be issues > since pci bridge will try to access some registers in the config which > may cause timeouts or Un clocked access as the power can be removed in > the suspend of pwrctl driver. > > To solve this make PCIe controller as parent to the pci pwr ctrl driver > and create devlink between host bridge and pci pwrctl driver so that > pci pwrctl driver will go suspend only after all the PCIe devices went > to suspend. > > In pci pwrctl driver use stop_link() to keep the link in D3cold and > start_link() to bring back link to D0. > > This series is developed on top the series: > https://lore.kernel.org/lkml/20240612082019.19161-1-brgl@bgdev.pl/ > > we are sending this series to get coments on the usage of stop_link > and start_link which is being add in this series. > > Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> > --- > Krishna chaitanya chundru (7): > dt: bindings: add qcom,qps615.yaml > arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node > pci: Change the parent of the platform devices for child OF nodes > pci: Add new start_link() & stop_link function ops > pci: dwc: Add support for new pci function op > pci: qcom: Add support for start_link() & stop_link() > pci: pwrctl: Add power control driver for qps615 > > .../devicetree/bindings/pci/qcom,qps615.yaml | 73 ++++++ > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++ > drivers/pci/bus.c | 5 +- > drivers/pci/controller/dwc/pcie-designware-host.c | 19 ++ > drivers/pci/controller/dwc/pcie-qcom.c | 108 +++++++- > drivers/pci/pwrctl/Kconfig | 7 + > drivers/pci/pwrctl/Makefile | 1 + > drivers/pci/pwrctl/core.c | 7 +- > drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++ > include/linux/pci.h | 2 + > 10 files changed, 541 insertions(+), 14 deletions(-) > --- > base-commit: d737627471e5b3962eedae870aa0475d6c9bba18 > change-id: 20240624-qps615-faa0cc60dc74 > > Best regards, > -- > Krishna chaitanya chundru <quic_krichai@quicinc.com> > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y qcom/qcs6490-rb3gen2.dtb' for 20240626-qps615-v1-0-2ade7bd91e02@quicinc.com: arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts:562.12-567.5: Warning (pci_device_reg): /soc@0/pcie@1c08000/pcie@0/qps615@0: PCI unit address format error, expected "2,0" arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts:560.3-27: Warning (pci_device_bus_num): /soc@0/pcie@1c08000/pcie@0/qps615@0:bus-range: PCI bus number 0 out of range, expected (1 - 255) arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dtb: rsc@18200000: 'qps615-0p9-vreg', 'qps615-1p8-vreg', 'qps615-rsex-vreg' do not match any of the regexes: '^regulators(-[0-9])?$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
On Wed, Jun 26, 2024 at 06:07:48PM +0530, Krishna chaitanya chundru wrote: > Krishna chaitanya chundru (7): > dt: bindings: add qcom,qps615.yaml > arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node > pci: Change the parent of the platform devices for child OF nodes > pci: Add new start_link() & stop_link function ops > pci: dwc: Add support for new pci function op > pci: qcom: Add support for start_link() & stop_link() > pci: pwrctl: Add power control driver for qps615 Take a look at the git history of the files you update and match the style. s/pci/PCI/, for instance.
QPS615 is the PCIe switch which has one upstream and three downstream ports. One of the downstream ports is used as endpoint device of Ethernet MAC. Other two downstream ports are supposed to connect to external device. One Host can connect to QPS615 by upstream port. QPS615 switch power is controlled by the GPIO's. After powering on the switch will immediately participate in the link training. if the host is also ready by that time PCIe link will established. The QPS615 needs to configured certain parameters like de-emphasis, disable unused port etc before link is established. These settings vary from platform to platform. As the controller starts link training before the probe of pwrctl driver, the PCIe link may come up before configuring the switch itself. To avoid this introduce two functions in pci_ops to start_link() & stop_link() which will disable the link training if the PCIe link is not up yet. Now PCI pwrctl device is the child of the pci-pcie bridge, if we want to enable the suspend resume for pwrctl device there may be issues since pci bridge will try to access some registers in the config which may cause timeouts or Un clocked access as the power can be removed in the suspend of pwrctl driver. To solve this make PCIe controller as parent to the pci pwr ctrl driver and create devlink between host bridge and pci pwrctl driver so that pci pwrctl driver will go suspend only after all the PCIe devices went to suspend. In pci pwrctl driver use stop_link() to keep the link in D3cold and start_link() to bring back link to D0. This series is developed on top the series: https://lore.kernel.org/lkml/20240612082019.19161-1-brgl@bgdev.pl/ we are sending this series to get coments on the usage of stop_link and start_link which is being add in this series. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> --- Krishna chaitanya chundru (7): dt: bindings: add qcom,qps615.yaml arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node pci: Change the parent of the platform devices for child OF nodes pci: Add new start_link() & stop_link function ops pci: dwc: Add support for new pci function op pci: qcom: Add support for start_link() & stop_link() pci: pwrctl: Add power control driver for qps615 .../devicetree/bindings/pci/qcom,qps615.yaml | 73 ++++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++ drivers/pci/bus.c | 5 +- drivers/pci/controller/dwc/pcie-designware-host.c | 19 ++ drivers/pci/controller/dwc/pcie-qcom.c | 108 +++++++- drivers/pci/pwrctl/Kconfig | 7 + drivers/pci/pwrctl/Makefile | 1 + drivers/pci/pwrctl/core.c | 7 +- drivers/pci/pwrctl/pci-pwrctl-qps615.c | 278 +++++++++++++++++++++ include/linux/pci.h | 2 + 10 files changed, 541 insertions(+), 14 deletions(-) --- base-commit: d737627471e5b3962eedae870aa0475d6c9bba18 change-id: 20240624-qps615-faa0cc60dc74 Best regards,