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Thu, 8 Aug 2024 14:03:59 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 8 Aug 2024 07:03:55 -0700 From: Luo Jie Subject: [PATCH 0/4] Add common PLL clock controller driver for IPQ9574 Date: Thu, 8 Aug 2024 22:03:11 +0800 Message-ID: <20240808-qcom_ipq_cmnpll-v1-0-b0631dcbf785@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAB/QtGYC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDCwML3cLk/Nz4zILC+OTcvIKcHF3zZENDQ8skI1MDY3MloK6CotS0zAq widGxtbUAlISBLWEAAAA= To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Konrad Dybcio CC: , , , , , , , , , , Luo Jie X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723125835; l=1714; i=quic_luoj@quicinc.com; s=20240808; h=from:subject:message-id; bh=Rgg4UP3uOFU/PU5X1arLl/LJ7lDSFFKnppjVFyV3iKQ=; b=MphMmobq0EAcRqXeWn095ni4rm1JYaClP9ZejPIFYUXLb2sW2rn8VkjpL2drXC6dwslD4sPzN UZM9wH9spxhB8Yj6E3VeJa7YkJcJXdApO2nfuOXZ/Fm5w/23XH6ULy2 X-Developer-Key: i=quic_luoj@quicinc.com; a=ed25519; pk=P81jeEL23FcOkZtXZXeDDiPwIwgAHVZFASJV12w3U6w= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: efyYWyX_UVRv2AzI22L3EbjAfLV5YTwp X-Proofpoint-GUID: efyYWyX_UVRv2AzI22L3EbjAfLV5YTwp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-08_14,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=848 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408080099 The common PLL clock controller in Qualcomm IPQ chipsets provides the clocks to the networking hardware blocks that are internal or external to the SoC. This driver configures the common PLL clock controller to enable the output clocks to such networking hardware blocks. These networking blocks include the internal PPE (Packet Process Engine), external connected Ethernet PHY, or external switch. The controller expects the input reference clock from the internal Wi-Fi block acting as the clock source. The output clocks supplied by the controller are fixed rate clocks. The driver is being enabled to support IPQ9574 SoC initially, and will be extended for other SoCs. Signed-off-by: Luo Jie --- Luo Jie (4): dt-bindings: clock: qcom: Add common PLL clock controller for IPQ SoC clk: qcom: Add common PLL clock controller driver for IPQ SoC arm64: defconfig: Enable Qualcomm IPQ common PLL clock controller arm64: dts: qcom: Add common PLL node for IPQ9574 SoC .../bindings/clock/qcom,ipq-cmn-pll.yaml | 87 ++++++++ arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 6 +- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 22 +- arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ipq-cmn-pll.c | 233 +++++++++++++++++++++ 7 files changed, 358 insertions(+), 2 deletions(-) --- base-commit: 222a3380f92b8791d4eeedf7cd750513ff428adf change-id: 20240808-qcom_ipq_cmnpll-7c1119b25037 Best regards,