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Fri, 13 Sep 2024 11:55:41 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Sep 2024 04:55:36 -0700 From: Lijuan Gao Subject: [PATCH v2 0/6] Add initial support for QCS615 SoC and QCS615 RIDE board Date: Fri, 13 Sep 2024 19:55:22 +0800 Message-ID: <20240913-add_initial_support_for_qcs615-v2-0-9236223e7dab@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIACoo5GYC/5XRwU7DMAwG4FeZcl5R7DRpshPvgVDVOimzBG2Xd BVo6ruTbggECG0cfx8+/4lPIoXIIYnd5iRimDnx0OeA242gfdM/hYJ9zgIlltKBLBrva+554ua 5TsdxHOJUd0OsD5QM6AIaZ0iVxlVoRUbGGDp+PS94eMx5z2ka4tt53wzr9EJbtNfoGQpZaO2cN S40ILv7w5GJe7qj4UWs+IxfoAO4CuIKylK1lUTrWv8N3H4+Gm+CbOmJTBkILfxupv7XTGUQKiK qfKd1J/9opm6CUKFvKw2KzI8/Wy4XiiFPE08fZ1qWdwxuUbQXAgAA To: , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thomas Gleixner" CC: , , , Lijuan Gao , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - QFPROM - TLMM - Watchdog - RPMH controller - Sleep stats driver This series are splited into three parts: - 1-3: Binding files for QCS615 SoC and PDC (Reviewed) - 4 : Soc table entry (Reviewed) - 5-6: Initial DTSI and RIDE board device tree Bindings Dependencies: watchdog: https://lore.kernel.org/all/20240912-add_watchdog_compatible_for_qcs615-v1-1-ec22b5ad9891@quicinc.com/ qfprom: https://lore.kernel.org/all/20240912-add_qfprom_compatible_for_qcs615-v1-1-9ef2e26c14ee@quicinc.com/ tcsr: https://lore.kernel.org/all/20240912-add_tcsr_compatible_for_qcs615-v1-1-5b85dd4d42ad@quicinc.com/ Build Dependencies: tlmm: https://lore.kernel.org/all/20240910-add_qcs615_pinctrl_driver-v1-0-36f4c0d527d8@quicinc.com/ Patch made the following verifications: - Successfully pass dt_binding_check with DT_CHECKER_FLAGS=-m for earch binding file - Successfully pass dtbs_check with W=1 for dts - Verified CPU Hotplug and online CPUs on QCS615 ride board - Checked pinctrl-maps path - Verified Watchdog functional with "echo 1 > /dev/watchdog", can trigger a watchdog bark and later bite - Verified functional with DCC console function on QCS615 ride board - RPMH controller driver probed successfully - Sleep stats driver probed successfully and checked qcom_stats node on QCS615 ride board Signed-off-by: Lijuan Gao --- Changes in v2: - Collected reviewed-bys - Removed extra blank line - Removed redundant function - Renamed xo-board to xo-board-clk and move it and sleep-clk to board dts - Renamed system-sleep to cluster_sleep_2 - Removed cluster1 - Added entry-method for idle-states - Added DTS chassis type - Added TCSR Clock Controllers - Added Reserved Shared memory - Added QFPROM - Added TLMM - Added Watchdog - Added RPMH controller - Added Sleep stats driver - Link to v1: https://lore.kernel.org/r/20240828-add_initial_support_for_qcs615-v1-0-5599869ea10f@quicinc.com --- Lijuan Gao (6): dt-bindings: arm: qcom: document QCS615 and the reference board dt-bindings: arm: qcom,ids: add SoC ID for QCS615 dt-bindings: qcom,pdc: document QCS615 Power Domain Controller soc: qcom: socinfo: Add QCS615 SoC ID table entry arm64: dts: qcom: add initial support for QCS615 DTSI arm64: dts: qcom: add base QCS615 RIDE dts Documentation/devicetree/bindings/arm/qcom.yaml | 6 + .../bindings/interrupt-controller/qcom,pdc.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs615-ride.dts | 34 ++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 511 +++++++++++++++++++++ drivers/soc/qcom/socinfo.c | 1 + include/dt-bindings/arm/qcom,ids.h | 1 + 7 files changed, 555 insertions(+) --- base-commit: 100cc857359b5d731407d1038f7e76cd0e871d94 change-id: 20240910-add_initial_support_for_qcs615-1a96c3469728 Best regards,