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[2001:14ba:a0c3:3a00:70b:e6fc:b322:6a1b]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53b2e1c901esm642356e87.219.2024.10.26.18.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Oct 2024 18:24:51 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH v5 00/11] clk: qcom: add support for clock controllers on the SAR2130P platform Date: Sun, 27 Oct 2024 03:24:39 +0200 Message-Id: <20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFiWHWcC/3XPwQrCMAwG4FeRnq0kaeumJ99DPHRrqkVZpZWhy N7dztOkePwD+f7kLTKnwFnsV2+ReAw5xKEEs16J/mKHM8vgShYEpBGwkdkmQgV32d9if83S+M6 5XedBM4uydU/sw/MrHk8lX0J+xPT6Fow4T/9bI0qQvjHcaPBgW3e4hcGmuInpLGZspAVAWANUA NUqNtwhKUsVoJaAqQFVAN16bDV5h2ZbAXoJbGtAzxc0CODKD9b1P8A0TR9seqSKcgEAAA== X-Change-ID: 20241017-sar2130p-clocks-5fbdd9bf04ee To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Neil Armstrong , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Kalpak Kawadkar , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3650; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=7tM/N1XH2DuKOmOBVNe95VBzXFxfDobIX6AJnVgmH/0=; b=owEBbQKS/ZANAwAKARTbcu2+gGW4AcsmYgBnHZZeEhUulsjctkQk+MwpZ4ZDh+dALftQ3exsW Ir+jth7k3CJAjMEAAEKAB0WIQRdB85SOKWMgfgVe+4U23LtvoBluAUCZx2WXgAKCRAU23LtvoBl uLu7D/oCMrWp8UQmOcTjas/Va59LwsbBlENgFF0VC3gth+la6dNy2e00d9zkQ+weAPEyoiMan8V L/rINmzYyyrs5W7JCi3pjKbUHvWB+undEWu/cYhwVP36S4gUZdpPqaL4/+GPc5pyj/InT/3aj2f JWFVeL8VyWczM8U0//V8W+NOGvILGYg9huSljEduQha4suDqRMXHBViQi1i8SEh4tdB9R0aKXTK 3TqgOMH7gewVlz9avOAyWkvw2uzpNhmDc6WZ8Ia55SisPwURU0RLmY3m7uqCR0psPK+rLa+P8Nm hlnTFgW6rBE+v371Ha+8wNQ3H4t+/6I/3otZJ5lP2jeh2x+J5+gUJJQg5ZKrHWmZhKbpHp8NxGj eabflV9HzP70TNmg8PdOEbtVkFfN3XvPu+ZWGyQ+1yLs6mc9pBtrVgZi93yrNISKeT9Uzf1gPHs w5Fn3xcqBNC7sOyVJ+Vx5v0kiWCzbiT9qrKa6XVWg9AhmQmzZHwi1ZaNVwI97IvXfKlVqNSfrLk Au3ZYXDpujx3m8cQxjCHLXou8YC5JmXqktphT0yqeNZHD6T86yw0FlS+f3VzGeI+HIGFF9Q1gO5 4ckWdQfJUxmfuwX4K24atZKa/lcxZBjhRy4/G1CzP6OtFvmwfJZqxRBBWVuyfIuPi2OfxAZiCY+ bcSZ7x9Mf8WG2aA== X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Add support for the RPMh, TCSR, Global, Display and GPU clock controllers as present on the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov --- Changes in v5: - Dropped the stray 'int ret' variable, leftover from the previous cleanup. - Link to v4: https://lore.kernel.org/r/20241026-sar2130p-clocks-v4-0-37100d40fadc@linaro.org Changes in v4: - Fixed commit message for the RPMh clocks patch to mention RF_CLK1 clock (Konrad) - Link to v3: https://lore.kernel.org/r/20241025-sar2130p-clocks-v3-0-48f1842fd156@linaro.org Changes in v3: - Added rfclka1 to RPMh clocks for SAR2140P (Taniya) - Added HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC, HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC, HLOS1_VOTE_TURING_MMU_TBU0_GDSC, HLOS1_VOTE_TURING_MMU_TBU1_GDSC (Taniya) - Removed extra debug print in gpucc probe (Konrad) - Link to v2: https://lore.kernel.org/r/20241021-sar2130p-clocks-v2-0-383e5eb123a2@linaro.org Changes in v2: - Dropped gcc_camera_hf_axi_clk, gcc_camera_sf_axi_clk, gcc_qmip_camera_nrt_ahb_clk, gcc_qmip_camera_rt_ahb_clk, gcc_iris_ss_hf_axi1_sreg, gcc_iris_ss_spd_axi1_sreg, gcc_video_axi0_sreg and gcc_video_axi1_sreg clocks until corresponding subsytems bringup (Taniya) - Program GDSC_SLEEP_ENA_VOTE directly from the probe function (Taniya) - Dropped sreg, BRANCH_HALT_POLL and collapse_sleep_mask patches (Taniya) - Dropped gcc_parent_data_4, gcc_parent_map_4, gcc_parent_data_5, gcc_parent_map_5 (LKP) - Link to v1: https://lore.kernel.org/r/20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org --- Dmitry Baryshkov (9): dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible dt-bindings: clock: qcom: document SAR2130P Global Clock Controller dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible clk: qcom: rcg2: add clk_rcg2_shared_floor_ops clk: qcom: rpmh: add support for SAR2130P clk: qcom: add support for GCC on SAR2130P clk: qcom: tcsrcc-sm8550: add SAR2130P support clk: qcom: dispcc-sm8550: enable support for SAR2130P Konrad Dybcio (2): dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles clk: qcom: add SAR2130P GPU Clock Controller support .../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + .../bindings/clock/qcom,sar2130p-gcc.yaml | 65 + .../bindings/clock/qcom,sm8450-gpucc.yaml | 2 + .../bindings/clock/qcom,sm8550-dispcc.yaml | 1 + .../bindings/clock/qcom,sm8550-tcsr.yaml | 1 + drivers/clk/qcom/Kconfig | 22 +- drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/clk-rcg.h | 1 + drivers/clk/qcom/clk-rcg2.c | 48 +- drivers/clk/qcom/clk-rpmh.c | 13 + drivers/clk/qcom/dispcc-sm8550.c | 18 +- drivers/clk/qcom/gcc-sar2130p.c | 2366 ++++++++++++++++++++ drivers/clk/qcom/gpucc-sar2130p.c | 502 +++++ drivers/clk/qcom/tcsrcc-sm8550.c | 18 +- include/dt-bindings/clock/qcom,sar2130p-gcc.h | 185 ++ include/dt-bindings/clock/qcom,sar2130p-gpucc.h | 33 + include/dt-bindings/reset/qcom,sar2130p-gpucc.h | 14 + 17 files changed, 3281 insertions(+), 11 deletions(-) --- base-commit: f6202e7cb4762be30b01ca4e1666512171c16d2a change-id: 20241017-sar2130p-clocks-5fbdd9bf04ee Best regards,