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Wed, 20 Nov 2024 10:59:57 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4AKAxvUn013586; Wed, 20 Nov 2024 10:59:57 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-mukhopad-hyd.qualcomm.com [10.147.244.250]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 4AKAxvSo013582; Wed, 20 Nov 2024 10:59:57 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 3978529) id 739AE5001C6; Wed, 20 Nov 2024 16:29:56 +0530 (+0530) From: Soutrik Mukhopadhyay To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: Soutrik Mukhopadhyay , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_riteshk@quicinc.com, quic_vproddut@quicinc.com, quic_abhinavk@quicinc.com Subject: [PATCH v4 0/2] Enable Display Port for Qualcomm SA8775P-ride platform Date: Wed, 20 Nov 2024 16:29:52 +0530 Message-Id: <20241120105954.9665-1-quic_mukhopad@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qJ30ILOu8raQ9akce61pUIEK4t-PVGcS X-Proofpoint-ORIG-GUID: qJ30ILOu8raQ9akce61pUIEK4t-PVGcS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=980 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411200076 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: This series adds the DPTX0 and DPTX1 nodes, as a part of mdss0 on Qualcomm SA8775P SoC. It also enables Display Port on Qualcomm SA8775P-ride platform. --- This patch depends on following series: https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0cef@quicinc.com/ https://lore.kernel.org/all/20241019-patchv3_1-v5-0-d2fb72c9a845@quicinc.com/ https://lore.kernel.org/all/20241018070706.28980-1-quic_mukhopad@quicinc.com/ v2: Fixed review comments from Dmitry, Konrad and Bjorn - Added a new patchset to separate out the soc and board parts.[Konrad] - Patchset 1 now comprises of the soc parts and patchset 2 includes board specific changes.[Bjorn] - Patchset 2 enables all the DP ports validated on the sa8775p-ride platform.[Bjorn] - Fixed indentation errors in the dtsi file containing the soc information.[Dmitry][Konrad] - Updated clocks to be used by respective PHYs.[Dmitry] - Added mdss0_dp1 device node.[Dmitry] - Updated the names of PHYs using label prefix "mdssM_dpN" for clarity.[Bjorn] - Avoided use of referring any label in the board(dts) file in the dtsi(platform) file.[Bjorn] v3: Fixed review comments from Dmitry and other minor changes to prevent warnings and maintain alignment - Added specific DP connector node for each DP port validated in patchset 2.[Dmitry] - Updated the reg value to 1 for port 1 under mdss_mdp in patchset 1. - Fixed the register address space for mdss0_dp1 and mdss0_dp1_phy in alignment to the register address space for mdss0_dp0 and mdss0_dp0_phy, in patchset 1. v4: Fixed review comments from Dmitry - Added p1 region to the register set of both mdss_dp0 and mdss_dp1 alongside validation of devicetree against DT schema.[Dmitry] --- Soutrik Mukhopadhyay (2): arm64: dts: qcom: sa8775p: add DisplayPort device nodes arm64: dts: qcom: sa8775p-ride: Enable Display Port arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 80 ++++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 218 ++++++++++++++++++++- 2 files changed, 297 insertions(+), 1 deletion(-)