| Message ID | 20241203-qcs8300_initial_dtsi-v4-0-d7c953484024@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add initial support for QCS8300 SoC and QCS8300 RIDE board | expand |
On Tue, 03 Dec 2024 17:27:11 +0800, Jingyi Wang wrote: > Introduce the Device Tree for the QCS8300 platform. > > Features added and enabled: > - CPUs with PSCI idle states > - Interrupt-controller with PDC wakeup support > - Timers, TCSR Clock Controllers > - Reserved Shared memory > - GCC and RPMHCC > - TLMM > - Interconnect > - QuP with uart > - SMMU > - QFPROM > - Rpmhpd power controller > - UFS > - Inter-Processor Communication Controller > - SRAM > - Remoteprocs including ADSP,CDSP and GPDSP > - BWMONs > > [...] Applied, thanks! [1/4] dt-bindings: arm: qcom: document QCS8300 SoC and reference board commit: d511280ce9cc5920442e78a589946f63c247dd3b [3/4] arm64: dts: qcom: add QCS8300 platform commit: 7be190e4bdd2bd1aca84afef06bb755c06a85473 [4/4] arm64: dts: qcom: add base QCS8300 RIDE board commit: 45d55e2da9bd10d24c4730b452b11a76dc3960b8 Best regards,
Introduce the Device Tree for the QCS8300 platform. Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs binding dependencies: - remoteproc: https://lore.kernel.org/linux-arm-msm/20240925-qcs8300_remoteproc_binding-v3-1-21b0c52b142b@quicinc.com/ - Reviewed - qfprom: https://lore.kernel.org/all/20240911-qcs8300_qfprom_binding-v2-1-d39226887493@quicinc.com/ - Reviewed - pdc: https://lore.kernel.org/all/20240911-qcs8300_binding-v2-1-de8641b3eaa1@quicinc.com/ - Reviewed Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com> --- Changes in v4: - fixup typo in Makefile(Andrew & Krzysztof) - add board name in the commit message of the defconfig change(Dmitry) - separate cpus into 2 clusters in cpu-map(Konrad) - use QCOM_ICC_TAG_ALWAYS instead of "0" for interconnect nodes(Konrad) - Remove unused labels and drop redundant comments(Konrad) - Move clocks to the dtsi file(Dmitry) - drop reviewed-by tag for dts patch for the code change - Link to v3: https://lore.kernel.org/r/20241128-qcs8300_initial_dtsi-v3-0-26aa8a164914@quicinc.com Changes in v3: - Update title and cleanup signed-off-by tag(Bjorn) - fix the INTID of EL2 non-secure physical timer(Cong) - add reviewed-by tag(except for the dtsi patch for the code change) - code rebase - Link to v2: https://lore.kernel.org/r/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com Changes in v2: - decoupled from the original series - Drop compatible for QCS8275 - fix property order and add line breaks - move sleep_clk node to qcs8300-ride.dts - move l3-cache nodes out of l2-cache nodes and remove cluster1/cluster2 - add BWMON nodes - commit-msg update - Link to v1: https://lore.kernel.org/r/20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com --- Jingyi Wang (4): dt-bindings: arm: qcom: document QCS8300 SoC and reference board arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 arm64: dts: qcom: add QCS8300 platform arm64: dts: qcom: add base QCS8300 RIDE board Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 235 ++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1405 +++++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + 5 files changed, 1650 insertions(+) --- base-commit: f486c8aa16b8172f63bddc70116a0c897a7f3f02 change-id: 20241128-qcs8300_initial_dtsi-ad3f193ce1d7 Best regards,