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Thu, 12 Dec 2024 09:24:18 GMT Received: from lijuang2-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 01:24:12 -0800 From: Lijuan Gao Subject: [PATCH 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300 Date: Thu, 12 Dec 2024 17:23:59 +0800 Message-ID: <20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAK+rWmcC/x2MQQqAIBAAvxJ7TsilKPpKhIhutheVNSKI/p51H JiZGwoJU4G5uUHo5MIpVtBtA263MZBiXxmww16j1solEXKHCZmTkc8oivxkcbAekUaoZRba+Pq vy/o8L/14FZdlAAAA To: Bjorn Andersson , Linus Walleij , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Jingyi Wang" , Konrad Dybcio CC: , , , , , Krzysztof Kozlowski , Lijuan Gao X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733995452; l=1516; i=quic_lijuang@quicinc.com; s=20240827; h=from:subject:message-id; bh=6E/T+GZ5juoXqET0Uv5nEv8S2NdF/YnTyLRun6ttthE=; b=UkpbjoW625oPEv/ILcZLPBMjVnya1NYP4EXRextdWohGRO61Oqpc9U67sTu4STeRagz7NFRK+ ed+sshQow09CBtSQqM27T2e1qhoYuVmQ9xhXiVvrEAd1UeDz8ATVYZ7 X-Developer-Key: i=quic_lijuang@quicinc.com; a=ed25519; pk=1zeM8FpQK/J1jSFHn8iXHeb3xt7F/3GvHv7ET2RNJxE= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jqWGCh8gCKNZgrLQP0h_wPmOZYPrS16z X-Proofpoint-GUID: jqWGCh8gCKNZgrLQP0h_wPmOZYPrS16z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=653 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120065 The UFS_RESET pin is expected to be wired to the reset pin of the primary UFS memory, it's a general purpose output pin. Reorder it and expose it as a gpio, so that the UFS driver can toggle it. The QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the gpio-rangs to 134. Signed-off-by: Lijuan Gao --- Lijuan Gao (6): dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615 dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300 pinctrl: qcom: correct the number of ngpios for QCS615 pinctrl: qcom: correct the number of ngpios for QCS8300 arm64: dts: qcom: correct gpio-ranges for QCS615 arm64: dts: qcom: correct gpio-ranges for QCS8300 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +- drivers/pinctrl/qcom/pinctrl-qcs615.c | 2 +- drivers/pinctrl/qcom/pinctrl-qcs8300.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) --- base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07 change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7 Best regards,