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Mon, 13 Jan 2025 17:27:12 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 13 Jan 2025 09:27:09 -0800 From: Taniya Das Subject: [PATCH 0/3] Add support to reconfigure PLL Date: Mon, 13 Jan 2025 22:57:03 +0530 Message-ID: <20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOdMhWcC/x3MTQqAIBBA4avErBvQfhZ2lWihNtVAqIwVQXT3p OW3eO+BTMKUYageELo4cwwFuq7AbzashDwXQ6OaXmndYj5TinJg2ncU8jEsvJ5CaKzxznWtNcp BqZPQwvd/Hqf3/QCeBKO3aQAAAA== X-Change-ID: 20250113-support-pll-reconfigure-9a9cbb43a90b To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _1wn0C6da59LsfoiIdYwdHfxy22F0meJ X-Proofpoint-GUID: _1wn0C6da59LsfoiIdYwdHfxy22F0meJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 mlxlogscore=925 mlxscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501130141 During boot-up, there is a possibility that the PLL configuration might be missed even after invoking pll_configure() from the clock controller probe. This is often due to the PLL being connected to rail or rails that are in an OFF state and current clock controller also cannot vote on multiple rails. As a result, the PLL may be enabled with suboptimal settings, leading to functional issues. The PLL configuration, now part of clk_alpha_pll, can be reused to reconfigure the PLL to a known good state before scaling for frequency. The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs in future. The IRIS driver support added https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/ observes the pll latch warning during boot up due to the dependency of the PLL not in good state, thus add config support for SM8550 Video clock controller PLLs. Signed-off-by: Taniya Das --- Taniya Das (3): clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure clk: qcom: clk-alpha-pll: Add support to reconfigure PLL clk: qcom: videocc-sm8550: Update the pll config for Video PLLs drivers/clk/qcom/clk-alpha-pll.c | 30 ++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 2 ++ drivers/clk/qcom/videocc-sm8550.c | 2 ++ 3 files changed, 34 insertions(+) --- base-commit: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc change-id: 20250113-support-pll-reconfigure-9a9cbb43a90b Best regards,