Message ID | 20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com (mailing list archive) |
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Sun, 19 Jan 2025 12:00:49 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50JC0mVD026192 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 19 Jan 2025 12:00:48 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 19 Jan 2025 04:00:44 -0800 From: Taniya Das <quic_tdas@quicinc.com> Subject: [PATCH v2 0/2] Add support for clock controllers and CPU scaling for QCS615 Date: Sun, 19 Jan 2025 17:30:26 +0530 Message-ID: <20250119-qcs615-mm-v2-dt-nodes-v2-0-c46ab4080989@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: <linux-arm-msm.vger.kernel.org> List-Subscribe: <mailto:linux-arm-msm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-arm-msm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; 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Add support for clock controllers and CPU scaling for QCS615
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Add the video, camera, display and gpu clock controller nodes and the cpufreq-hw node to support cpu scaling. Clock Dependency: https://lore.kernel.org/all/20250119-qcs615-mm-v4-clockcontroller-v4-0-5d1bdb5a140c@quicinc.com/ Changes in v2: - pad address field to 8 digits [Dmitry] - Replace cpu/CPU in commit [Dmitry] - Update the binding to use SC7180 compatible, as QCS615 uses the same hardware version. - Link to v1: https://lore.kernel.org/r/20241108-qcs615-mm-dt-nodes-v1-0-b2669cac0624@quicinc.com Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- Taniya Das (2): arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock arm64: dts: qcom: qcs615: Add CPU scaling clock node arch/arm64/boot/dts/qcom/qcs615.dtsi | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) --- base-commit: 0907e7fb35756464aa34c35d6abb02998418164b change-id: 20250119-qcs615-mm-v2-dt-nodes-d5d924bee55e prerequisite-message-id: <20250119-qcs615-mm-v4-clockcontroller-v4-0-5d1bdb5a140c@quicinc.com> prerequisite-patch-id: 72a894a3b19fdbd431e1cec9397365bc5b27abfe prerequisite-patch-id: 7fa9f2a44f98280ae6639924c8ce08a89457170d prerequisite-patch-id: b9e3a2663e27dc60be0eff97baf3739db8516eeb prerequisite-patch-id: cb93e5798f6bfe8cc3044c4ce973e3ae5f20dc6b prerequisite-patch-id: faf0d569634dad432f67acd073343e47add0ee68 prerequisite-patch-id: 807019bedabd47c04f7ac78e9461d0b5a6e9131b prerequisite-patch-id: 1a1dbf7144745dfbc60c0f2efcad188d1fc26779 prerequisite-patch-id: 125bb8cb367109ba22cededf6e78754579e1ed03 prerequisite-patch-id: b12e39a6a0763b8ec23c99c82f3ac6acdca26f85 prerequisite-patch-id: 71f0eb0fb98c3177dcbe6736c120cba4efef0c33 Best regards,