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Wed, 29 Jan 2025 01:43:50 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-438dcc81589sm16035205e9.33.2025.01.29.01.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jan 2025 01:43:49 -0800 (PST) From: Neil Armstrong Subject: [PATCH v3 0/2] arm64: dts: qcom: sm8650: rework CPU & GPU thermal zones Date: Wed, 29 Jan 2025 10:43:44 +0100 Message-Id: <20250129-topic-sm8650-thermal-cpu-idle-v3-0-62ab1a64098d@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFD4mWcC/43NQQ6CMBCF4auQrq3pFBHqynsYF6UdYBKgpMVGQ 7i7hZWudPm/TL5ZWEBPGNglW5jHSIHcmCI/ZMx0emyRk03NpJCFAJHz2U1keBiqcyH43KEfdM/ N9Eh3PXJAUFCBVie0LBmTx4aeu3+7p+4ozM6/9ncRtvVfOQIXvNEaGgGAxqprT6P27uh8yzY6y g8OxC9OJq4oq1LbUum6rr+4dV3f4mWMoRoBAAA= X-Change-ID: 20250103-topic-sm8650-thermal-cpu-idle-1e19181a94ed To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE On the SM8650 platform, the dynamic clock and voltage scaling (DCVS) for the CPUs is handled by hardware & firmware using factory and form-factor determined parameters in order to maximize frequency while keeping the temperature way below the junction temperature where the SoC would experience a thermal shutdown if not permanent damages. On the other side, the High Level Ooperating System (HLOS), like Linux, is able to adjust the CPU and GPU frequency using the internal SoC temperature sensors (here tsens) and it's UP/LOW interrupts, but it effectly does the same work twice for CPU in an less effective manner. Let's take the CPU Hardware & Firmware action in account and design the thermal zones trip points and cooling devices mapping to use the HLOS as a safety warant in case the platform experiences a temperature surge to helpfully avoid a thermal shutdown and handle the scenario gracefully. On the CPU side, the LMh hardware does the DCVS control loop, so only keep the critical trip point that would do a software system reboot as an emergency action to avoid the thermal shutdown. On the GPU side, the GPU can achieve much higher temperature, update the trip point with the downstream implementation as a reference. Those 2 changes optimizes the thermal management design by avoiding concurrent thermal management, calculations & avoidable interrupts for CPU, and allows us to use reach higher OPPs for the GPUs and squeeze more performances in both cases. Signed-off-by: Neil Armstrong --- Changes in v3: - The GMU doesn't handle temperature, remove it from all texts, just bump the temps - Link to v2: https://lore.kernel.org/r/20250110-topic-sm8650-thermal-cpu-idle-v2-0-5787ad79abbb@linaro.org Changes in v2: - Drop idle injection - only keep critical trip points - reword commmit msg and cover letter - Link to v1: https://lore.kernel.org/r/20250103-topic-sm8650-thermal-cpu-idle-v1-0-faa1f011ecd9@linaro.org --- Neil Armstrong (2): arm64: dts: qcom: sm8650: drop cpu thermal passive trip points arm64: dts: qcom: sm8650: setup gpu thermal with higher temperatures arch/arm64/boot/dts/qcom/sm8650.dtsi | 228 ++++------------------------------- 1 file changed, 24 insertions(+), 204 deletions(-) --- base-commit: 8155b4ef3466f0e289e8fcc9e6e62f3f4dceeac2 change-id: 20250103-topic-sm8650-thermal-cpu-idle-1e19181a94ed Best regards,