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Thu, 20 Mar 2025 05:55:08 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 52K5t8oR001130; Thu, 20 Mar 2025 05:55:08 GMT Received: from cbsp-sh-gv.ap.qualcomm.com (CBSP-SH-gv.ap.qualcomm.com [10.231.249.68]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 52K5t7OA001129 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Mar 2025 05:55:08 +0000 Received: by cbsp-sh-gv.ap.qualcomm.com (Postfix, from userid 4635958) id A686340BF8; Thu, 20 Mar 2025 13:55:03 +0800 (CST) From: Wenbin Yao To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, quic_qianyu@quicinc.com, sfr@canb.auug.org.au, linux-arm-kernel@lists.infradead.org Cc: quic_wenbyao@quicinc.com Subject: [PATCH v1 0/3] arm64: qcom: x1e80100-qcp: Add power supply and sideband signals config for PCIe3 Date: Thu, 20 Mar 2025 13:54:59 +0800 Message-Id: <20250320055502.274849-1-quic_wenbyao@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iK5GldEBxZYqyFOTGGLzZadHVGdOCQRo X-Authority-Analysis: v=2.4 cv=MJ5gmNZl c=1 sm=1 tr=0 ts=67dbadbe cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=Vs1iUdzkB0EA:10 a=oy1NtThjofowiJkyXhQA:9 X-Proofpoint-ORIG-GUID: iK5GldEBxZYqyFOTGGLzZadHVGdOCQRo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-20_01,2025-03-19_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=702 clxscore=1011 spamscore=0 priorityscore=1501 mlxscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503200035 The first patch enable the PCI Power Control driver to control the power state of PCI slots. The second patch add the bus topology of PCIe domain 3 on x1e80100 platform. The third patch add perst, wake and clkreq sideband signals, and describe the regulators powering the rails of the PCI slots in the devicetree for PCIe3 controller and PHY device. Qiang Yu (3): arm64: defconfig: enable PCI Power Control for PCIe3 arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 arm64: dts: qcom: x1e80100-qcp: Add power control and sideband signals for PCIe3 arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 119 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++ arch/arm64/configs/defconfig | 1 + 3 files changed, 130 insertions(+) base-commit: 0a2f889128969dab41861b6e40111aa03dc57014