mbox series

[0/4] Add CMN PLL clock controller support for IPQ5424

Message ID 20250321-qcom_ipq5424_cmnpll-v1-0-3ea8e5262da4@quicinc.com (mailing list archive)
Headers show
Series Add CMN PLL clock controller support for IPQ5424 | expand

Message

Jie Luo March 21, 2025, 12:49 p.m. UTC 
The CMN PLL block of IPQ5424 is almost same as that of IPQ9574
which is currently supported by the driver. The only difference
is that the fixed output clocks to NSS and PPE from CMN PLL have
a different clock rate. In IPQ5424, the output clocks are supplied
to NSS at 300 MHZ and to PPE at 375 MHZ.

Two related clock identifiers NSS_300MHZ_CLK and PPE_375MHZ_CLK
are added for IPQ5424. The new table of output clocks is added
for the CMN PLL of IPQ5424, which is acquired from the device
according to the compatible.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
Luo Jie (4):
      dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
      clk: qcom: cmnpll: Add IPQ5424 SoC support
      arm64: dts: ipq5424: Add CMN PLL node
      arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock

 .../bindings/clock/qcom,ipq9574-cmn-pll.yaml       |  1 +
 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts        | 23 +++++++++++++--
 arch/arm64/boot/dts/qcom/ipq5424.dtsi              | 27 ++++++++++++++++-
 drivers/clk/qcom/ipq-cmn-pll.c                     | 34 ++++++++++++++++++----
 include/dt-bindings/clock/qcom,ipq-cmn-pll.h       | 10 ++++++-
 5 files changed, 86 insertions(+), 9 deletions(-)
---
base-commit: 9388ec571cb1adba59d1cded2300eeb11827679c
change-id: 20250321-qcom_ipq5424_cmnpll-416f770f2f97

Best regards,