Message ID | cover.1603448364.git.saiprakash.ranjan@codeaurora.org (mailing list archive) |
---|---|
Headers | show
Return-Path: <SRS0=y8wr=EB=vger.kernel.org=linux-arm-msm-owner@kernel.org> Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3FE1697 for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 26 Oct 2020 11:54:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C291A22265 for <patchwork-linux-arm-msm@patchwork.kernel.org>; Mon, 26 Oct 2020 11:54:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="Jp0U0QMH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1774079AbgJZLyT (ORCPT <rfc822;patchwork-linux-arm-msm@patchwork.kernel.org>); Mon, 26 Oct 2020 07:54:19 -0400 Received: from z5.mailgun.us ([104.130.96.5]:28744 "EHLO z5.mailgun.us" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1774075AbgJZLyT (ORCPT <rfc822;linux-arm-msm@vger.kernel.org>); Mon, 26 Oct 2020 07:54:19 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1603713257; h=Content-Transfer-Encoding: MIME-Version: Message-Id: Date: Subject: Cc: To: From: Sender; bh=szGp3b/hhWRxwpJshGTpSP+kxFDoTXvVtB0VW0Yh+A4=; b=Jp0U0QMHCbYDx5+7Nx0WA9dVMvn0pLRxikdhnHJnCMaRwKMvAxDoPXM5adRgqV16HaruEzkj nLccLtO1UeSlCxg0wa9UVMhT/OvwtWA3kpsdk5yEQBk3Ga/uCpJLHPqlu+3EveiZ/Lc4BfT0 H6A5UpNyHTcmqyI6oFMzCsoaMi0= X-Mailgun-Sending-Ip: 104.130.96.5 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 5f96b8e867b50553e26089aa (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 26 Oct 2020 11:54:16 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 30D15C43382; Mon, 26 Oct 2020 11:54:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00,SPF_FAIL, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-253.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3FA89C433C9; Mon, 26 Oct 2020 11:54:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3FA89C433C9 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=saiprakash.ranjan@codeaurora.org From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> To: Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>, Jordan Crouse <jcrouse@codeaurora.org>, Rob Clark <robdclark@gmail.com> Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Akhil P Oommen <akhilpo@codeaurora.org>, freedreno@lists.freedesktop.org, "Kristian H . Kristensen" <hoegsberg@google.com>, dri-devel@lists.freedesktop.org, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Subject: [PATCHv6 0/6] System Cache support for GPU and required SMMU support Date: Mon, 26 Oct 2020 17:23:59 +0530 Message-Id: <cover.1603448364.git.saiprakash.ranjan@codeaurora.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: <linux-arm-msm.vger.kernel.org> X-Mailing-List: linux-arm-msm@vger.kernel.org |
Series |
System Cache support for GPU and required SMMU support
|
expand
|