From patchwork Fri Nov 22 23:32:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 11258643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E26D91390 for ; Fri, 22 Nov 2019 23:32:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C0D772073F for ; Fri, 22 Nov 2019 23:32:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="CJH71qHD"; dkim=pass (1024-bit key) header.d=amazonses.com header.i=@amazonses.com header.b="f9qs1BAe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726638AbfKVXcS (ORCPT ); Fri, 22 Nov 2019 18:32:18 -0500 Received: from a27-55.smtp-out.us-west-2.amazonses.com ([54.240.27.55]:55932 "EHLO a27-55.smtp-out.us-west-2.amazonses.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726998AbfKVXcH (ORCPT ); Fri, 22 Nov 2019 18:32:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=zsmsymrwgfyinv5wlfyidntwsjeeldzt; d=codeaurora.org; t=1574465526; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; bh=81ys/5oVCzoSQIqDE8l251BF02aMdA0az+eobjsIwPs=; b=CJH71qHDG3b5RwgfbxN18nXxyXKdrh4FD352asbk11jFtz98NP76SB5CIyA9vVDJ GYChHJ14BIrta4uJOfzLjjyIkq1WfW4DqGe1MNTSgNNaqL8N3hYLGXWK/36t0zKEOqR xu4OBNdxW4zKPOMkQWMvRnO9pTPquJOKEf3Z/dsI= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=gdwg2y3kokkkj5a55z2ilkup5wp5hhxx; d=amazonses.com; t=1574465526; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:Feedback-ID; bh=81ys/5oVCzoSQIqDE8l251BF02aMdA0az+eobjsIwPs=; b=f9qs1BAePVbhzpRpxBswaRb7MHIwUTuJ1tW234jTy+sFQvMDvKS7AVqmIjNnwsjz VcjFqvy+sncuibVgi2pIDwM3iM4Xv+Zrst8HgIPL91LyGSSJ8NSccebmnanWi2ppkkN E/kndiyE2ikBghZqtVsIjOdgUwBjmkjgwFTTVFe0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A71CEC76F67 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: iommu@lists.linux-foundation.org Cc: robin.murphy@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Sean Paul , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Rob Clark , David Airlie , freedreno@lists.freedesktop.org, Mamta Shukla , Daniel Vetter Subject: [PATCH v2 7/8] drm/msm/a6xx: Support split pagetables Date: Fri, 22 Nov 2019 23:32:06 +0000 Message-ID: <0101016e95755c4a-0b41bbd3-8d15-418a-a1d6-a135726b4d03-000000@us-west-2.amazonses.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org> References: <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org> X-SES-Outgoing: 2019.11.22-54.240.27.55 Feedback-ID: 1.us-west-2.CZuq2qbDmUIuT3qdvXlRHZZCpfZqZ4GtG9v3VKgRyF0=:AmazonSES Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Attempt to enable split pagetables if the arm-smmu driver supports it. This will move the default address space from the default region to the address range assigned to TTBR1. The behavior should be transparent to the driver for now but it gets the default buffers out of the way when we want to start swapping TTBR0 for context-specific pagetables. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5dc0b2c..96b3b28 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -811,6 +811,50 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; } +static struct msm_gem_address_space * +a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) +{ + struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type); + struct msm_gem_address_space *aspace; + struct msm_mmu *mmu; + u64 start, size; + u32 val = 1; + int ret; + + if (!iommu) + return ERR_PTR(-ENOMEM); + + /* Try to request split pagetables */ + iommu_domain_set_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val); + + mmu = msm_iommu_new(&pdev->dev, iommu); + if (IS_ERR(mmu)) { + iommu_domain_free(iommu); + return ERR_CAST(mmu); + } + + /* Check to see if split pagetables were successful */ + ret = iommu_domain_get_attr(iommu, DOMAIN_ATTR_SPLIT_TABLES, &val); + if (!ret && val) { + /* + * The aperture start will be at the beginning of the TTBR1 + * space so use that as a base + */ + start = iommu->geometry.aperture_start; + size = 0xffffffff; + } else { + /* Otherwise use the legacy 32 bit region */ + start = SZ_16M; + size = 0xffffffff - SZ_16M; + } + + aspace = msm_gem_address_space_create(mmu, "gpu", start, size); + if (IS_ERR(aspace)) + iommu_domain_free(iommu); + + return aspace; +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -832,7 +876,7 @@ static const struct adreno_gpu_funcs funcs = { #if defined(CONFIG_DRM_MSM_GPU_STATE) .gpu_state_get = a6xx_gpu_state_get, .gpu_state_put = a6xx_gpu_state_put, - .create_address_space = adreno_iommu_create_address_space, + .create_address_space = a6xx_create_address_space, #endif }, .get_timestamp = a6xx_get_timestamp,