diff mbox series

[5/5] arm: dts: sc7180: Add A618 gpu dt blob

Message ID 0101016ecc556508-b3be0a5f-4987-4c21-a0b4-33f380cf278b-000000@us-west-2.amazonses.com (mailing list archive)
State New, archived
Headers show
Series Add support for A618 GPU | expand

Commit Message

Sharat Masetty Dec. 3, 2019, 3:16 p.m. UTC 
This patch adds the required dt nodes and properties
to enabled A618 GPU.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

--
1.9.1

Comments

Matthias Kaehlcke Dec. 4, 2019, 10 p.m. UTC | #1 
Hi Sharat,

on which tree is this patch based on? It does not apply against qcom/arm64-for-5.6-to-be-rebased.

In one of my repos which has a non-upstream Qualcomm tree as remote git can
make sense of the hashes in the index line, however the parent of your patch
looks quite different from the maintainer version.

Another thing that hints towards a custom tree:

> +			interconnects = <&gem_noc 35 &mc_virt 512>;

To my knowledge no patches have been posted to add the referenced interconnect
nodes for SC7180.

Please base your patches on the appropriate maintainer tree(s).

Thanks

Matthias

On Tue, Dec 03, 2019 at 03:16:18PM +0000, Sharat Masetty wrote:
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
> 
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++++++++++++++++++++++++++++++++++
>  1 file changed, 116 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index c3db2e5..31223d0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -18,6 +18,8 @@
>  #include <dt-bindings/reset/qcom,sdm845-pdc.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
> +#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> 
>  / {
>  	interrupt-parent = <&intc>;
> @@ -733,6 +735,120 @@
>  			#power-domain-cells = <1>;
>  		};
> 
> +		gpu: gpu@5000000 {
> +			compatible = "qcom,adreno-618.0", "qcom,adreno";
> +			#stream-id-cells = <16>;
> +			reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>,
> +				<0 0x5061000 0 0x800>;
> +			reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
> +
> +			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			iommus = <&adreno_smmu 0>;
> +
> +			operating-points-v2 = <&gpu_opp_table>;
> +
> +			interconnects = <&gem_noc 35 &mc_virt 512>;
> +
> +			qcom,gmu = <&gmu>;
> +
> +			gpu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-800000000 {
> +					opp-hz = /bits/ 64 <800000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> +				};
> +
> +				opp-650000000 {
> +					opp-hz = /bits/ 64 <650000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +				};
> +
> +				opp-565000000 {
> +					opp-hz = /bits/ 64 <565000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +				};
> +
> +				opp-430000000 {
> +					opp-hz = /bits/ 64 <430000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +				};
> +
> +                                opp-355000000 {
> +					opp-hz = /bits/ 64 <355000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +				};
> +
> +                                opp-267000000 {
> +					opp-hz = /bits/ 64 <267000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +				};
> +
> +				opp-180000000 {
> +					opp-hz = /bits/ 64 <180000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
> +		adreno_smmu: iommu@5040000 {
> +			compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> +			reg = <0 0x5040000 0 0x10000>;
> +			#iommu-cells = <1>;
> +			#global-interrupts = <2>;
> +			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
> +					<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
> +					<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
> +			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> +				<&gcc GCC_GPU_CFG_AHB_CLK>,
> +				<&gcc GCC_DDRSS_GPU_AXI_CLK>;
> +
> +			clock-names = "bus", "iface", "mem_iface_clk";
> +			power-domains = <&gpucc CX_GDSC>;
> +		};
> +
> +		gmu: gmu@506a000 {
> +			compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
> +
> +			reg = 	<0 0x506a000 0 0x31000>,
> +				<0 0xb290000 0 0x10000>,
> +				<0 0xb490000 0 0x10000>;
> +			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
> +
> +			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "hfi", "gmu";
> +
> +			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> +			       <&gpucc GPU_CC_CXO_CLK>,
> +			       <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> +			       <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
> +			clock-names = "gmu", "cxo", "axi", "memnoc";
> +
> +			power-domains = <&gpucc CX_GDSC>;
> +
> +			iommus = <&adreno_smmu 5>;
> +
> +			operating-points-v2 = <&gmu_opp_table>;
> +
> +			gmu_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-200000000 {
> +					opp-hz = /bits/ 64 <200000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> +				};
> +			};
> +		};
> +
>  		apps_smmu: iommu@15000000 {
>  			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
>  			reg = <0 0x15000000 0 0x100000>;
> --
> 1.9.1
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c3db2e5..31223d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -18,6 +18,8 @@ 
 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
+#include <dt-bindings/power/qcom-rpmpd.h>

 / {
 	interrupt-parent = <&intc>;
@@ -733,6 +735,120 @@ 
 			#power-domain-cells = <1>;
 		};

+		gpu: gpu@5000000 {
+			compatible = "qcom,adreno-618.0", "qcom,adreno";
+			#stream-id-cells = <16>;
+			reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x1000>,
+				<0 0x5061000 0 0x800>;
+			reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			interconnects = <&gem_noc 35 &mc_virt 512>;
+
+			qcom,gmu = <&gmu>;
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-800000000 {
+					opp-hz = /bits/ 64 <800000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+				};
+
+				opp-650000000 {
+					opp-hz = /bits/ 64 <650000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+				};
+
+				opp-565000000 {
+					opp-hz = /bits/ 64 <565000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+				};
+
+				opp-430000000 {
+					opp-hz = /bits/ 64 <430000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				};
+
+                                opp-355000000 {
+					opp-hz = /bits/ 64 <355000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+                                opp-267000000 {
+					opp-hz = /bits/ 64 <267000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+
+				opp-180000000 {
+					opp-hz = /bits/ 64 <180000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
+		adreno_smmu: iommu@5040000 {
+			compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+			reg = <0 0x5040000 0 0x10000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <2>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+				<&gcc GCC_GPU_CFG_AHB_CLK>,
+				<&gcc GCC_DDRSS_GPU_AXI_CLK>;
+
+			clock-names = "bus", "iface", "mem_iface_clk";
+			power-domains = <&gpucc CX_GDSC>;
+		};
+
+		gmu: gmu@506a000 {
+			compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
+
+			reg = 	<0 0x506a000 0 0x31000>,
+				<0 0xb290000 0 0x10000>,
+				<0 0xb490000 0 0x10000>;
+			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi", "gmu";
+
+			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+			       <&gpucc GPU_CC_CXO_CLK>,
+			       <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+			       <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+			clock-names = "gmu", "cxo", "axi", "memnoc";
+
+			power-domains = <&gpucc CX_GDSC>;
+
+			iommus = <&adreno_smmu 5>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-200000000 {
+					opp-hz = /bits/ 64 <200000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				};
+			};
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;