| Message ID | 066299506138ffcf1a3135b6f1a4609eee46ddf9.1691660905.git.quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable IPQ5332 USB2 | expand |
On 10/08/2023 11:56, Varadarajan Narayanan wrote: > Add USB phy and controller nodes. > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v6: > Remove clock names > Move the nodes to address sorted location > v5: > Use generic phy instead of usb-phy > 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check' passed > 'DT_CHECKER_FLAGS='-v -m' DT_SCHEMA_FILES=qcom dt_binding_check' passed > v4: > Change node name > Remove blank line > 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed > v1: > Rename phy node > Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy > Remove 'qscratch' from phy node > Fix alignment and upper-case hex no.s > Add clock definition for the phy > Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() > in dwc3/core.c takes the frequency from ref clock and calculates fladj > as appropriate. > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 55 +++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 8bfc2db..c45d9d4 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -145,6 +145,19 @@ > #size-cells = <1>; > ranges = <0 0 0 0xffffffff>; > > + usbphy0: phy@7b000 { > + compatible = "qcom,ipq5332-usb-hsphy"; > + reg = <0x0007b000 0x12c>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > qfprom: efuse@a4000 { > compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; > reg = <0x000a4000 0x721>; > @@ -290,6 +303,48 @@ > status = "disabled"; > }; > > + usb: usb2@8a00000 { usb@ Node names must be generic. > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; > + reg = <0x08af8800 0x400>; OK, so this was not really checked for any warnings. It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db..c45d9d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -145,6 +145,19 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + usbphy0: phy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; @@ -290,6 +303,48 @@ status = "disabled"; }; + usb: usb2@8a00000 { + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + + clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "core", + "iface", + "sleep", + "mock_utmi"; + + resets = <&gcc GCC_USB_BCR>; + + qcom,select-utmi-as-pipe-clk; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + usb2_0_dwc: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x08a00000 0xe000>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + phy-names = "usb2-phy"; + phys = <&usbphy0>; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */
Add USB phy and controller nodes. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> --- v6: Remove clock names Move the nodes to address sorted location v5: Use generic phy instead of usb-phy 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check' passed 'DT_CHECKER_FLAGS='-v -m' DT_SCHEMA_FILES=qcom dt_binding_check' passed v4: Change node name Remove blank line 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed v1: Rename phy node Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy Remove 'qscratch' from phy node Fix alignment and upper-case hex no.s Add clock definition for the phy Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() in dwc3/core.c takes the frequency from ref clock and calculates fladj as appropriate. --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)