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Fri, 16 Jun 2023 19:02:56 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%7]) with mapi id 15.20.6477.037; Fri, 16 Jun 2023 19:02:56 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v4 10/25] iommu/exynos: Implement an IDENTITY domain Date: Fri, 16 Jun 2023 16:02:39 -0300 Message-Id: <10-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v4-874277bde66e+1a9f6-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR20CA0065.namprd20.prod.outlook.com (2603:10b6:208:235::34) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS7PR12MB5912:EE_ X-MS-Office365-Filtering-Correlation-Id: e049e19d-6e84-4967-571f-08db6e9c4ac4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WdCY7A7BDQ1ctE4FThDhVjfEnxJv/FlHtyFY2VKwQSqJklCJtQblDYJVB9fvU3HtLjhfDDEf+/eUPYevn6kvoS24OvpueOr2cODSvWe7gpCguOdmUPAZEZuP4N1hERVq2Gim7dT8fxWOSuHmq0pXvKXR24yCH8jRaaQAbFOLSGWinzRnDHv+4BDy7lb73pOXziYERgk1Qe01NdDO5ta9ALJGlRt3et/5w9zqLgIWRpqkPSLnFr5ZNkjvO5HTdaLcjzpV5F8++W3DxLaO3goDJChhAcVdP//hYch1tx1GAOnUauEai9UdQgDKxItj6JS22BIJO7GHa/ngurAPmGJR9UCOUr5PnQMHpenk0LsMsBg/ePmpNTCV6NEEIirxRWcEayambgfXm0rGj/rF/c14DKQp5797HV+86vMzV1i+NeQ/E4+naPkuq7zehpNq09Y78iSBMO67neJhI10MmfqWT9piQ47TM491iWLUFnIcb08gdLVB679y/p9+oTHGplQ7r/BDcp4ps1jsBZjDbp140hESBBaSxq7Q5ewa9xOvJ8xZzvkxJ1UozbM8x5hTl3WpQBo4jTS10VZKw2hszqWis3lYmk+xL5CvZmoo1DgyQqTq9/yJumwcL6nH4KMwN1ZJvbUrFB8d+BdCAYPEQixr3K50SFcPKdDPCWCcy3EpQIiM61v7nxu37Sx7EKhwEBd5uOusZgN3xyMc002z70mNBjp+czBzLsFBxvofioPXmhUOg6OyjXHQBBUKOO/sbn1vV7EhEqT7jrEyq3qbu/F+bzjxYPNV27C3vQTunAjc/jS0cQcQQ2gJFz+R2ZkFdZ4DuXUkSmv0aUcvGqnwFwdNeFKeLczkqlT0W/vhkYrUr9/D+K+PcJdkgDqp35Y1V5PCEshxcwKYCJaDcQM+v1W/l302RtK3dUEoZeCN2OClKBr0my5lWN0X9tqRKQmJVlJ2wlskIdv3RVLqWaFQ45Lff8kOIXVuQJs6IFHvfftczcOz58MiWb/O9y0P3tvrM1qHXmfj95uyoWa84S227l/AQKaYVHVVJuRvWip8CxyJsz4xzeasj1X+zSSk9JTGRe2mOBGD4vGDZofKT47jj6zrWPpGwtL8GweFEBOvt0kr16mwlfInMxJ5puolHLK3m6GlCUTzZ+0DfJuh8AjxOoCMEnkTWz19fp8trkjXQ5EzXTwoUybBrvVCRYp0ufEEI/WPUh5kZggKWxIrFj1GpvyNRlPBPD3eiefTf2t8ynGpPNCDzjo6zpVRVuwtwAklKj1QNsDb67wiQwwgZKLzzXN7nxEj80y9/v14fklFFgOv7xV7PGCPBXSKqccIxUpFOh8Om1cCN0Idzn5p3FQKhl//gz9vSnV0ENaQVjCTQc6IcWUmmC9k8xOU5Z8VwSUVi3RRLd3q1Glx4JHG5gFqtMGus79bWN6120En/BBalubZrBUe54VwmpdJjhVk0G0s0Ug2Ru5JGm5xZJb8geZJWwxIifK0xPmG3SHVEQ743HzmCJ0m43zd54Ro6I2QGSjfE6fz0jvjxtVZDkmNAfBtMA03z0DdfdGHHat/Yh2i91ia/6zMfjTLliXgJSCstEYun5OM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e049e19d-6e84-4967-571f-08db6e9c4ac4 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2023 19:02:55.2685 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HOm1zmd4F1Jvq9cB1F3RTZDjKvXajoqXOYfF0wwN8jZlrgsrtrLGCqeyUfC4emVC X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5912 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org What exynos calls exynos_iommu_detach_device is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. Tested-by: Marek Szyprowski Acked-by: Marek Szyprowski Signed-off-by: Jason Gunthorpe --- drivers/iommu/exynos-iommu.c | 66 +++++++++++++++++------------------- 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c275fe71c4db32..5e12b85dfe8705 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -24,6 +24,7 @@ typedef u32 sysmmu_iova_t; typedef u32 sysmmu_pte_t; +static struct iommu_domain exynos_identity_domain; /* We do not consider super section mapping (16MB) */ #define SECT_ORDER 20 @@ -829,7 +830,7 @@ static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); - if (data->domain) { + if (&data->domain->domain != &exynos_identity_domain) { dev_dbg(data->sysmmu, "saving state\n"); __sysmmu_disable(data); } @@ -847,7 +848,7 @@ static int __maybe_unused exynos_sysmmu_resume(struct device *dev) struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); - if (data->domain) { + if (&data->domain->domain != &exynos_identity_domain) { dev_dbg(data->sysmmu, "restoring state\n"); __sysmmu_enable(data); } @@ -980,17 +981,20 @@ static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) kfree(domain); } -static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, - struct device *dev) +static int exynos_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { - struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - phys_addr_t pagetable = virt_to_phys(domain->pgtable); + struct exynos_iommu_domain *domain; + phys_addr_t pagetable; struct sysmmu_drvdata *data, *next; unsigned long flags; - if (!has_sysmmu(dev) || owner->domain != iommu_domain) - return; + if (owner->domain == identity_domain) + return 0; + + domain = to_exynos_domain(owner->domain); + pagetable = virt_to_phys(domain->pgtable); mutex_lock(&owner->rpm_lock); @@ -1009,15 +1013,25 @@ static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, list_del_init(&data->domain_node); spin_unlock(&data->lock); } - owner->domain = NULL; + owner->domain = identity_domain; spin_unlock_irqrestore(&domain->lock, flags); mutex_unlock(&owner->rpm_lock); - dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, - &pagetable); + dev_dbg(dev, "%s: Restored IOMMU to IDENTITY from pgtable %pa\n", + __func__, &pagetable); + return 0; } +static struct iommu_domain_ops exynos_identity_ops = { + .attach_dev = exynos_iommu_identity_attach, +}; + +static struct iommu_domain exynos_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &exynos_identity_ops, +}; + static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, struct device *dev) { @@ -1026,12 +1040,11 @@ static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, struct sysmmu_drvdata *data; phys_addr_t pagetable = virt_to_phys(domain->pgtable); unsigned long flags; + int err; - if (!has_sysmmu(dev)) - return -ENODEV; - - if (owner->domain) - exynos_iommu_detach_device(owner->domain, dev); + err = exynos_iommu_identity_attach(&exynos_identity_domain, dev); + if (err) + return err; mutex_lock(&owner->rpm_lock); @@ -1407,26 +1420,12 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) return &data->iommu; } -static void exynos_iommu_set_platform_dma(struct device *dev) -{ - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - - if (owner->domain) { - struct iommu_group *group = iommu_group_get(dev); - - if (group) { - exynos_iommu_detach_device(owner->domain, dev); - iommu_group_put(group); - } - } -} - static void exynos_iommu_release_device(struct device *dev) { struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data; - exynos_iommu_set_platform_dma(dev); + WARN_ON(exynos_iommu_identity_attach(&exynos_identity_domain, dev)); list_for_each_entry(data, &owner->controllers, owner_node) device_link_del(data->link); @@ -1457,6 +1456,7 @@ static int exynos_iommu_of_xlate(struct device *dev, INIT_LIST_HEAD(&owner->controllers); mutex_init(&owner->rpm_lock); + owner->domain = &exynos_identity_domain; dev_iommu_priv_set(dev, owner); } @@ -1471,11 +1471,9 @@ static int exynos_iommu_of_xlate(struct device *dev, } static const struct iommu_ops exynos_iommu_ops = { + .identity_domain = &exynos_identity_domain, .domain_alloc = exynos_iommu_domain_alloc, .device_group = generic_device_group, -#ifdef CONFIG_ARM - .set_platform_dma_ops = exynos_iommu_set_platform_dma, -#endif .probe_device = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,