| Message ID | 1376485183-2664-2-git-send-email-iivanov@mm-sol.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 08/14/2013 06:59 AM, Ivan T. Ivanov wrote: > From: "Ivan T. Ivanov" <iivanov@mm-sol.com> > > MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys > (SNPS) and HS, SS PHY's control and configuration registers. > > It could operate in device mode (SS, HS, FS) and host > mode (SS, HS, FS, LS). > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt > +- clock-names : ... > + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low ... > + "ref_clk" : Reference clock - used in host mode. ... > + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS ... > + "iface_clk" : System bus AXI clock > + "sleep_clk" : Sleep clock, used when USB3 core goes into low ... > + "utmi_clk" : Generated by HS-PHY. Used to clock the low power I think it makes sense to remove "_clk" from all those names, unless the HW documentation really talks about a clock named e.g. iface_clk yet some other clock names in the documentation don't have the "_clk" suffix, e.g. the "xo I didn't quote. > +Sub nodes: > +========== That section title is the same style as all the other section title, so it's no obvious that this is a sub-node for the controller wrapper. Instead, I would suggest something more like: Required child nodes: > +- Sub node for "DWC3 USB3 controller". Then you can drop that since it's obvious. > + This sub node is required property for device node. The properties > + of this subnode are specified in dwc3.txt. That doesn't really say much. How about. ---------- A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. ---------- -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Fri, 2013-08-16 at 16:44 -0600, Stephen Warren wrote: > On 08/14/2013 06:59 AM, Ivan T. Ivanov wrote: > > From: "Ivan T. Ivanov" <iivanov@mm-sol.com> > > > > MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys > > (SNPS) and HS, SS PHY's control and configuration registers. > > > > It could operate in device mode (SS, HS, FS) and host > > mode (SS, HS, FS, LS). > > > diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt > > > +- clock-names : > ... > > + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low > ... > > + "ref_clk" : Reference clock - used in host mode. > ... > > + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS > ... > > + "iface_clk" : System bus AXI clock > > + "sleep_clk" : Sleep clock, used when USB3 core goes into low > ... > > + "utmi_clk" : Generated by HS-PHY. Used to clock the low power > > I think it makes sense to remove "_clk" from all those names, unless the > HW documentation really talks about a clock named e.g. iface_clk yet > some other clock names in the documentation don't have the "_clk" > suffix, e.g. the "xo I didn't quote. From limited information that I have, I could not say how clock inputs are named from the controller perspective, but I agree that "_clk" suffix looks redundant. Side question: if for example label in controller says "UTMI", should I also use capital letters for the resource or this could be "utmi"? > > > +Sub nodes: > > +========== > > That section title is the same style as all the other section title, so > it's no obvious that this is a sub-node for the controller wrapper. > Instead, I would suggest something more like: > > Required child nodes: > > > +- Sub node for "DWC3 USB3 controller". > > Then you can drop that since it's obvious. > > > + This sub node is required property for device node. The properties > > + of this subnode are specified in dwc3.txt. > > That doesn't really say much. How about. > > ---------- > A child node must exist to represent the core DWC3 IP block. The name of > the node is not important. The content of the node is defined in dwc3.txt. > ---------- Thanks, I will use your suggestion. Regards, Ivan -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 08/19/2013 06:27 AM, Ivan T. Ivanov wrote: > > Hi, > > On Fri, 2013-08-16 at 16:44 -0600, Stephen Warren wrote: >> On 08/14/2013 06:59 AM, Ivan T. Ivanov wrote: >>> From: "Ivan T. Ivanov" <iivanov@mm-sol.com> >>> >>> MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys >>> (SNPS) and HS, SS PHY's control and configuration registers. >>> >>> It could operate in device mode (SS, HS, FS) and host >>> mode (SS, HS, FS, LS). >> >>> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt >> >>> +- clock-names : >> ... >>> + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low >> ... >>> + "ref_clk" : Reference clock - used in host mode. >> ... >>> + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS >> ... >>> + "iface_clk" : System bus AXI clock >>> + "sleep_clk" : Sleep clock, used when USB3 core goes into low >> ... >>> + "utmi_clk" : Generated by HS-PHY. Used to clock the low power >> >> I think it makes sense to remove "_clk" from all those names, unless the >> HW documentation really talks about a clock named e.g. iface_clk yet >> some other clock names in the documentation don't have the "_clk" >> suffix, e.g. the "xo I didn't quote. > > From limited information that I have, I could not say how clock inputs > are named from the controller perspective, but I agree that "_clk" > suffix looks redundant. > > Side question: if for example label in controller says "UTMI", should I > also use capital letters for the resource or this could be "utmi"? All the clock-names entries I've seen so far have been lower-case, but I suppose there's no hard-and-fast rule that they couldn't be upper-/mixed-case if that best matched the HW documentation. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 08/19/13 05:27, Ivan T. Ivanov wrote: > Hi, > > On Fri, 2013-08-16 at 16:44 -0600, Stephen Warren wrote: >> On 08/14/2013 06:59 AM, Ivan T. Ivanov wrote: >>> From: "Ivan T. Ivanov" <iivanov@mm-sol.com> >>> >>> MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys >>> (SNPS) and HS, SS PHY's control and configuration registers. >>> >>> It could operate in device mode (SS, HS, FS) and host >>> mode (SS, HS, FS, LS). >>> diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt >>> +- clock-names : >> ... >>> + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low >> ... >>> + "ref_clk" : Reference clock - used in host mode. >> ... >>> + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS >> ... >>> + "iface_clk" : System bus AXI clock >>> + "sleep_clk" : Sleep clock, used when USB3 core goes into low >> ... >>> + "utmi_clk" : Generated by HS-PHY. Used to clock the low power >> I think it makes sense to remove "_clk" from all those names, unless the >> HW documentation really talks about a clock named e.g. iface_clk yet >> some other clock names in the documentation don't have the "_clk" >> suffix, e.g. the "xo I didn't quote. > From limited information that I have, I could not say how clock inputs > are named from the controller perspective, but I agree that "_clk" > suffix looks redundant. In downstream trees we've tried to standardize the names on core_clk, iface_clk, bus_clk, etc. Historically the hardware designers have used the names from the clock controller instead of coming up with standard names of their own when they put the clock inputs in their data sheets (if they do at all).
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt new file mode 100644 index 0000000..43c73d8 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt @@ -0,0 +1,108 @@ +MSM SuperSpeed DWC3 USB SoC controller + + +DWC3 Highspeed USB PHY +====================== +Required properities : +- compatible : sould be "qcom,dwc3-hsphy"; +- reg : offset and length of the register set in the memory map +- clocks : phandles to clock instances of the device tree nodes +- clock-names : + "xo" : External reference clock 19 MHz + "sleep_a_clk" : Sleep clock, used when USB3 core goes into low + power mode (U3). +<supply-name>-supply : phandle to the regulator device tree node +Required "supply-name" are: + "v1p8" : 1.8v supply for HSPHY + "v3p3" : 3.3v supply for HSPHY + "vbus" : vbus supply for host mode + "vddcx" : vdd supply for HS-PHY digital circuit operation + +DWC3 Superspeed USB PHY +======================= +Required properities : +- compatible : sould be "qcom,dwc3-ssphy"; +- reg : offset and length of the register set in the memory map +- clocks : phandles to clock instances of the device tree nodes +- clock-names : + "xo" : External reference clock 19 MHz + "ref_clk" : Reference clock - used in host mode. +<supply-name>-supply : phandle to the regulator device tree node +Required "supply-name" are: + "v1p8" : 1.8v supply for SS-PHY + "vddcx" : vdd supply for SS-PHY digital circuit operation + +DWC3 controller wrapper +======================= +Required properties : +- compatible : should be "qcom,dwc3" +- reg : offset and length of the register set in the memory map + offset and length of the TCSR register for routing USB + signals to either picoPHY0 or picoPHY1. +- clocks : phandles to clock instances of the device tree nodes +- clock-names : + "core_clk" : Master/Core clock, have to be >= 125 MHz for SS + operation and >= 60MHz for HS operation + "iface_clk" : System bus AXI clock + "sleep_clk" : Sleep clock, used when USB3 core goes into low + power mode (U3). + "utmi_clk" : Generated by HS-PHY. Used to clock the low power + parts of thr HS Link layer. +Optional properties : +- gdsc-supply : phandle to the globally distributed switch controller + regulator node to the USB controller. + + +Sub nodes: +========== +- Sub node for "DWC3 USB3 controller". + This sub node is required property for device node. The properties + of this subnode are specified in dwc3.txt. + +Example device nodes: + + dwc3_hsphy: phy@f92f8800 { + compatible = "qcom,dwc3-hsphy"; + reg = <0xf92f8800 0x30>; + + clocks = <&cxo>, <&usb2a_phy_sleep_cxc>; + clock-names = "xo", "sleep_a_clk"; + + vbus-supply = <&supply>; + vddcx-supply = <&supply>; + v1p8-supply = <&supply>; + v3p3-supply = <&supply>; + }; + + dwc3_ssphy: phy@f92f8830 { + compatible = "qcom,dwc3-ssphy"; + reg = <0xf92f8830 0x30>; + + clocks = <&cxo>, <&usb30_mock_utmi_cxc>; + clock-names = "xo", "ref_clk"; + + vddcx-supply = <&supply>; + v1p8-supply = <&supply>; + }; + + usb@fd4ab000 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfd4ab000 0x4>; + + clocks = <&usb30_master_cxc>, <&sys_noc_usb3_axi_cxc>, + <&usb30_sleep_cxc>, <&usb30_mock_utmi_cxc>; + clock-names = "core_clk", "iface_clk", "sleep_clk", "utmi_clk"; + + gdsc-supply = <&supply>; + + ranges; + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcd00>; + interrupts = <0 131 0>; + usb-phy = <&dwc3_hsphy>, <&dwc3_ssphy>; + tx-fifo-resize; + }; + };