From patchwork Tue Apr 29 08:20:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4085831 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AA4409F169 for ; Tue, 29 Apr 2014 08:22:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D88F8201F2 for ; Tue, 29 Apr 2014 08:22:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0513A20155 for ; Tue, 29 Apr 2014 08:22:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932731AbaD2IUv (ORCPT ); Tue, 29 Apr 2014 04:20:51 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:41955 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932596AbaD2IUq (ORCPT ); Tue, 29 Apr 2014 04:20:46 -0400 Received: by mail-wi0-f179.google.com with SMTP id z2so7354wiv.0 for ; Tue, 29 Apr 2014 01:20:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vzhPQyFzWM3xiOSLiTRv9ql26Mt5MOVhCz29QkxMFKg=; b=etKUwrM+IzhVf+B5JHhm9xOf3Svunf6N6daup7egbzBwFQQa16kghfQZDkl2nKXYjc NGGwUvJQnVauGzsOHRQrLZt3wXYGGcr84b7zAMeE4ASBzsvuezsXyNYYF8b5TZuG30gi vbG3YFx1+Efn9R0RJq4iox/UrdfmuQD4RY1jD/VyLjPwvhU99jIQAa5/niR/Z2Tnm0OI uo3DyrpjHp/RjMDbsPQzRSei4VqDA8R2zoXr/UvrOfK4rSfYeWzdZwonBhLA93tr/TCn 1p7H41Mx0ZnJx5sjvj/b6SVc0QtP4ixANvwOrJSwEjJzYLI+qMblJZjHeNexXjfJBPio uSfQ== X-Gm-Message-State: ALoCoQllmPPaqKNAGLLFcFexG2JUQhsC4XgKTFXTAQIaOm7/uMqsMZaieQBgYIu8uBh9SXdRLPnO X-Received: by 10.194.6.106 with SMTP id z10mr22781696wjz.1.1398759644857; Tue, 29 Apr 2014 01:20:44 -0700 (PDT) Received: from srinivas-Inspiron-N5050.dlink.com (host-78-147-6-229.as13285.net. [78.147.6.229]) by mx.google.com with ESMTPSA id w6sm29952632wjq.29.2014.04.29.01.20.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 29 Apr 2014 01:20:44 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , linux-mmc@vger.kernel.org Cc: Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v1 08/11] mmc: mmci: Qcom fix MCICLK register settings. Date: Tue, 29 Apr 2014 09:20:37 +0100 Message-Id: <1398759638-13299-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla MCICLK register layout is bit different to the standard pl180 register layout. Qcom SDCC controller some setup in MCICLK register to get it going. So this patch adds new setup and makes it specific to Qcom hw designer. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 36 ++++++++++++++++++++++++++++++------ drivers/mmc/host/mmci.h | 21 +++++++++++++++++++++ 2 files changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 306e0c8..35aed38 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -326,13 +326,37 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) /* Set actual clock for debug */ host->mmc->actual_clock = host->cclk; - if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) - clk |= MCI_4BIT_BUS; - if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + if (host->hw_designer == AMBA_VENDOR_QCOM) { + clk |= MCI_CLK_QCOM_FLOWENA; + clk |= (MCI_CLK_QCOM_SEL_FEEDBACK_CLK << + MCI_CLK_QCOM_SEL_IN_SHIFT); /* feedback clk */ + if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) + clk |= MCI_CLK_QCOM_WIDEBUS_8; + else if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) + clk |= MCI_CLK_QCOM_WIDEBUS_4; + else + clk |= MCI_CLK_QCOM_WIDEBUS_1; + + if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) { + /* clear SELECT_IN field */ + clk &= ~(MCI_CLK_QCOM_SEL_MASK << + MCI_CLK_QCOM_SEL_IN_SHIFT); + /* set DDR timing mode */ + clk |= (MCI_CLK_QCOM_SEL_DDR_MODE << + MCI_CLK_QCOM_SEL_IN_SHIFT); + } + clk |= (MCI_CLK_SDC4_MCLK_SEL_MCLK << + MCI_CLK_SDC4_MCLK_SEL_SHIFT); - if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) - clk |= MCI_ST_UX500_NEG_EDGE; + } else { + if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) + clk |= MCI_4BIT_BUS; + if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) + clk |= MCI_ST_8BIT_BUS; + + if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) + clk |= MCI_ST_UX500_NEG_EDGE; + } mmci_write_clkreg(host, clk); } diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 58b1b88..0a6de1c 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -31,6 +31,27 @@ /* Modified PL180 on Versatile Express platform */ #define MCI_ARM_HWFCEN (1 << 12) +/* Modified on Qualcomm Integrations */ +#define MCI_CLK_QCOM_WIDEBUS_1 (0 << 10) +#define MCI_CLK_QCOM_WIDEBUS_4 (2 << 10) +#define MCI_CLK_QCOM_WIDEBUS_8 (3 << 10) +#define MCI_CLK_QCOM_FLOWENA (1 << 12) +#define MCI_CLK_QCOM_INVERTOUT (1 << 13) + +/* select in latch data and command */ +#define MCI_CLK_QCOM_SEL_IN_SHIFT (14) +#define MCI_CLK_QCOM_SEL_MASK (0x3) +#define MCI_CLK_QCOM_SEL_RISING_EDGE (1) +#define MCI_CLK_QCOM_SEL_FEEDBACK_CLK (2) +#define MCI_CLK_QCOM_SEL_DDR_MODE (3) + +/* mclk selection */ +#define MCI_CLK_SDC4_MCLK_SEL_SHIFT (23) +#define MCI_CLK_SDC4_MCLK_SEL_MASK (0x3) +#define MCI_CLK_SDC4_MCLK_SEL_FB_CLK (1) +#define MCI_CLK_SDC4_MCLK_SEL_MCLK (2) + + #define MMCIARGUMENT 0x008 #define MMCICOMMAND 0x00c #define MCI_CPSM_RESPONSE (1 << 6)