From patchwork Tue Apr 29 08:20:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4085811 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BBBFBBFF02 for ; Tue, 29 Apr 2014 08:22:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F171A201F5 for ; Tue, 29 Apr 2014 08:22:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 155BA20155 for ; Tue, 29 Apr 2014 08:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932817AbaD2IVD (ORCPT ); Tue, 29 Apr 2014 04:21:03 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:44568 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932815AbaD2IU7 (ORCPT ); Tue, 29 Apr 2014 04:20:59 -0400 Received: by mail-wi0-f174.google.com with SMTP id d1so6965858wiv.13 for ; Tue, 29 Apr 2014 01:20:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9Bn+oLscYyIhTQzgeWud3hiuATNvxrsE+lIuVnoSkxw=; b=NQemW5AXGYWgLiMmJdy6rtVSmwLQH8W6IGgLDpF7yEkCyaSpsbFhzVt229PNvyZGEy 8gMTHQJqHuNILw3T4oGjjVl4pIuhj6rqGuwI6Eb63/RZQVjzTdwNNewR2nQrNCW90eog /gH+Ar68SM0ktn7hIr3+WrGoibe/ktlmOgbVRmin8TmCyWwkNSratrye9zgbze3A6uTR CfqcG92uwcHG9BN/QHZQmGJgrkgpZkBAG2wBBtGlH0ivOKe2i0fRVGYv4wAgZmmKWrfn OG0LDNHaeIqaKDrEdPazMxnVYoViiBkXZ4+XHhowbWPL2XNYr2SQfbg0GnREhvT4vhzA JO1Q== X-Gm-Message-State: ALoCoQm/FrEJ5xi4/qAFL7JJY91zf+PMYLtSEkT3rBZkp3l/+kPW+4ldQXYHvcvUIOTD8UUrmY4l X-Received: by 10.180.228.42 with SMTP id sf10mr18993516wic.33.1398759658401; Tue, 29 Apr 2014 01:20:58 -0700 (PDT) Received: from srinivas-Inspiron-N5050.dlink.com (host-78-147-6-229.as13285.net. [78.147.6.229]) by mx.google.com with ESMTPSA id pm5sm29968679wjc.11.2014.04.29.01.20.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 29 Apr 2014 01:20:57 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , linux-mmc@vger.kernel.org Cc: Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v1 09/11] mmc: mmci: Add clock support for Qualcomm. Date: Tue, 29 Apr 2014 09:20:51 +0100 Message-Id: <1398759651-13341-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla MCICLK going to card bus is directly driven by the clock controller, so the driver has to set the required rates depending on the state of the card. This bit of support is very much similar to bypass mode but there is no such thing called bypass mode in MCICLK register of Qcom SD card controller. By default the clock is directly driven by the clk controller. This patch adds clock support for Qualcomm SDCC in the driver. This bit of code is conditioned on hw designer. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 35aed38..da135c0 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -290,7 +290,10 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) host->cclk = 0; if (desired) { - if (desired >= host->mclk) { + + if (host->hw_designer == AMBA_VENDOR_QCOM) { + host->cclk = host->mclk; + } else if (desired >= host->mclk) { clk = MCI_CLK_BYPASS; if (variant->st_clkdiv) clk |= MCI_ST_UX500_NEG_EDGE; @@ -1371,6 +1374,19 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (!ios->clock && variant->pwrreg_clkgate) pwr &= ~MCI_PWR_ON; + if (ios->clock != host->mclk && + host->hw_designer == AMBA_VENDOR_QCOM) { + /* Qcom MCLKCLK register does not define bypass bits */ + int rc = clk_set_rate(host->clk, ios->clock); + if (rc < 0) { + dev_err(mmc_dev(host->mmc), + "Error setting clock rate (%d)\n", rc); + } else { + host->mclk = clk_get_rate(host->clk); + host->cclk = host->mclk; + } + } + spin_lock_irqsave(&host->lock, flags); mmci_set_clkreg(host, ios->clock); @@ -1611,7 +1627,8 @@ static int mmci_probe(struct amba_device *dev, * of course. */ if (plat->f_max) - mmc->f_max = min(host->mclk, plat->f_max); + mmc->f_max = (host->hw_designer == AMBA_VENDOR_QCOM) ? + plat->f_max : min(host->mclk, plat->f_max); else mmc->f_max = min(host->mclk, fmax); dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);