From patchwork Thu May 15 09:37:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4180481 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 29212BFF02 for ; Thu, 15 May 2014 09:40:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 24CB92035D for ; Thu, 15 May 2014 09:40:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 406D120306 for ; Thu, 15 May 2014 09:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754586AbaEOJhc (ORCPT ); Thu, 15 May 2014 05:37:32 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:51652 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754486AbaEOJhV (ORCPT ); Thu, 15 May 2014 05:37:21 -0400 Received: by mail-wi0-f170.google.com with SMTP id bs8so281482wib.1 for ; Thu, 15 May 2014 02:37:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RWsP/2UJrRJf115inaZ0m72DB/S3vgU+MzOTol6vjRs=; b=THUHQvtcR7uPV7D1/IFaUImC/dPfEBNSLDFr4P5ufFuUOH0lkJkGQqddHj27/J3dYF R8l7eSl0OVRtQSKUQwezUHzTckZZ2cqDjH4lZx+8uTYQnh+KH9IXmuiy7dG1uCDK9p4p X2NDAplQfNG2aYjzutUFdHXrBnRXTuq+anglU4nOvRx/5vn/rx4Uzjzd9REDIj+rE4Zt hs2P+3UilD3DMPSuMQaWK/Io+zDe/U+p6oK7F3Wxr+ZC5G5UcOkqAWihnqiF5HLnvBt+ yEoGxvcMMmm/LnB/bcO+gbqxruyOnZv6OTXgpDJw6ZmZNhesvksvAA9BMw0U/MgEtb6D nokw== X-Gm-Message-State: ALoCoQnpS8cllDna3JIUIul7bx7OoBxpDWMdfrUzKc+Bp/zPcYaXXmiFV0+ZLec8oyriV769dx/2 X-Received: by 10.194.78.4 with SMTP id x4mr1583352wjw.58.1400146640027; Thu, 15 May 2014 02:37:20 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-145-240-98.as13285.net. [78.145.240.98]) by mx.google.com with ESMTPSA id z19sm609141wiu.0.2014.05.15.02.37.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 May 2014 02:37:19 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v2 08/14] mmc: mmci: add 8bit bus support in variant data Date: Thu, 15 May 2014 10:37:16 +0100 Message-Id: <1400146636-30138-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds 8bit bus enable to variant structure giving more flexibility to the driver to support more SOCs which have different clock register layout. Without this patch other new SOCs like Qcom will have to add more code to special case them. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index dec70d2..a81f303 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -52,6 +52,7 @@ static unsigned int fmax = 515633; * struct variant_data - MMCI variant-specific quirks * @clkreg: default value for MCICLOCK register * @clkreg_enable: enable value for MMCICLOCK register + * @clkreg_8bit_bus_enable: enable value for 8 bit bus * @datalength_bits: number of bits in the MMCIDATALENGTH register * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY * is asserted (likewise for RX) @@ -74,6 +75,7 @@ static unsigned int fmax = 515633; struct variant_data { unsigned int clkreg; unsigned int clkreg_enable; + unsigned int clkreg_8bit_bus_enable; unsigned int datalength_bits; unsigned int fifosize; unsigned int fifohalfsize; @@ -116,6 +118,7 @@ static struct variant_data variant_u300 = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg_enable = MCI_ST_U300_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 16, .sdio = true, @@ -144,6 +147,7 @@ static struct variant_data variant_ux500 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -160,6 +164,7 @@ static struct variant_data variant_ux500v2 = { .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, .clkreg_enable = MCI_ST_UX500_HWFCEN, + .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, .datalength_bits = 24, .sdio = true, @@ -340,7 +345,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) - clk |= MCI_ST_8BIT_BUS; + clk |= variant->clkreg_8bit_bus_enable; if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) clk |= MCI_ST_UX500_NEG_EDGE;