From patchwork Thu May 15 09:37:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 4180471 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6217B9F3A0 for ; Thu, 15 May 2014 09:39:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 528412035D for ; Thu, 15 May 2014 09:39:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 52F8420306 for ; Thu, 15 May 2014 09:39:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754709AbaEOJhh (ORCPT ); Thu, 15 May 2014 05:37:37 -0400 Received: from mail-we0-f181.google.com ([74.125.82.181]:59779 "EHLO mail-we0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753408AbaEOJhf (ORCPT ); Thu, 15 May 2014 05:37:35 -0400 Received: by mail-we0-f181.google.com with SMTP id w61so764165wes.40 for ; Thu, 15 May 2014 02:37:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VFSWVj266UAk8sJ6eV1GxTrBhOqJgUNIBBbhRRX5Xyg=; b=hZmQbYZ6Qqs+bgzWqos58Tz1JLoYbkRZ6xxvcWdT4EGBzOIO5gGk+cPKdV7QuEkgJI bMd1/IsjGbzJP324rXtuNgbJoEBD2HNHCRf8usHeFTukDwESBZUyQDvxC0PvY4nqHTN1 EGRJ0S3Fb9Ok9uQo2aAz/JhFyAed1+AQtpIX9I1iKa73z9bKBCA7xU4IebC9xTtsNo0u Vi78d0PrEbpVsLpVtIs+MhBFBA6WSHeWrIs99bJ4fSDrhphylZRkJB2qUNdcdQwG2/hv 0aFJM/TYHXCL1lob+a1NzdvtR6PwwcPzqDkl2etPWXJ4EfNOH5Mo0G9Rt3Y0F3JKXLdF dugw== X-Gm-Message-State: ALoCoQlc7o/7Ux5H4dWER2+Z3tpX36TDpARVB7gpgb184H/2+S7aEDQqfdgmGUOTn0pSQkwVP/St X-Received: by 10.180.8.66 with SMTP id p2mr30476928wia.37.1400146654305; Thu, 15 May 2014 02:37:34 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-145-240-98.as13285.net. [78.145.240.98]) by mx.google.com with ESMTPSA id be3sm6071373wjc.5.2014.05.15.02.37.32 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 May 2014 02:37:33 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v2 10/14] mmc: mmci: add Qcom specifics of clk and datactrl registers. Date: Thu, 15 May 2014 10:37:31 +0100 Message-Id: <1400146651-30220-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds specifics of clk and datactrl register on Qualcomm SD Card controller. This patch also populates the Qcom variant data with these new values specific to Qualcomm SD Card Controller. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 3 +++ drivers/mmc/host/mmci.h | 24 ++++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 17e7f6a..0a0fc22 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -185,6 +185,9 @@ static struct variant_data variant_qcom = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, + .clkreg_enable = MCI_QCOM_CLK_FLOWENA, + .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, + .datactrl_mask_ddrmode = MCI_QCOM_CLK_DDR_MODE, .blksz_datactrl4 = true, .datalength_bits = 24, .blksz_datactrl4 = true, diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index cd83ca3..1b93ae7 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -41,6 +41,22 @@ /* Modified PL180 on Versatile Express platform */ #define MCI_ARM_HWFCEN BIT(12) +/* Modified on Qualcomm Integrations */ +#define MCI_QCOM_CLK_WIDEBUS_4 (2 << 10) +#define MCI_QCOM_CLK_WIDEBUS_8 (3 << 10) +#define MCI_QCOM_CLK_FLOWENA BIT(12) +#define MCI_QCOM_CLK_INVERTOUT BIT(13) + +/* select in latch data and command */ +#define MCI_QCOM_CLK_SEL_IN_SHIFT (14) +#define MCI_QCOM_CLK_SEL_MASK (0x3) +#define MCI_QCOM_CLK_SEL_RISING_EDGE (1) +#define MCI_QCOM_CLK_FEEDBACK_CLK (2 << 14) +#define MCI_QCOM_CLK_DDR_MODE (3 << 14) + +/* mclk selection */ +#define MCI_QCOM_CLK_SEL_MCLK (2 << 23) + #define MMCIARGUMENT 0x008 #define MMCICOMMAND 0x00c #define MCI_CPSM_RESPONSE BIT(6) @@ -54,6 +70,14 @@ #define MCI_ST_NIEN BIT(13) #define MCI_ST_CE_ATACMD BIT(14) +/* Modified on Qualcomm Integrations */ +#define MCI_QCOM_CSPM_DATCMD BIT(12) +#define MCI_QCOM_CSPM_MCIABORT BIT(13) +#define MCI_QCOM_CSPM_CCSENABLE BIT(14) +#define MCI_QCOM_CSPM_CCSDISABLE BIT(15) +#define MCI_QCOM_CSPM_AUTO_CMD19 BIT(16) +#define MCI_QCOM_CSPM_AUTO_CMD21 BIT(21) + #define MMCIRESPCMD 0x010 #define MMCIRESPONSE0 0x014 #define MMCIRESPONSE1 0x018